MULTI-DIMENSIONAL DATA REGISTRATION INTEGRATED CIRCUIT FOR DRIVING ARRAY-ARRANGEMENT DEVICES

• US 20090316195A1
• Filed: 06/08/2009
• Published: 12/24/2009
• Est. Priority Date: 06/20/2008
• Status: Active Grant

• Current Assignee: National Tsing Hua University
• Original Assignee: National Tsing Hua University
• Inventors: LIOU, JIAN CHIUN, TSENG, FAN GANG
• Granted Patent: US 8,625,153 B2
• Time in Patent Office: Days
• US Class Current: 358/1.150
• CPC Class Codes: B41J 2/04541 Specific driving circuit
• CPC Class Codes: B41J 2/04586 controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type

Abstract

A multi-dimensional data registration integrated circuit is configured for driving array-arrangement devices. The array-arrangement devices comprise a plurality of first hierarchy sets, each which comprises a plurality of second hierarchy sets. The multi-dimensional data registration integrated circuit comprises a first hierarchy address selection circuit, a second hierarchy address selection circuit and a data supply circuit. The first hierarchy address selection circuit scans the first hierarchy sets, and selects a unit of the first hierarchy sets to activate it. The second hierarchy address selection circuit scans the second hierarchy sets. The data supply circuit writes a plurality of data into each designated unit of the second hierarchy sets according to the scanning sequence of the second hierarchy address selection circuit.

Claims

1. A multi-dimensional data registration integrated circuit for driving array-arrangement devices divided into a plurality of first hierarchy sets, each of which comprises a plurality of second hierarchy sets, comprising:

a first hierarchy address selection circuit scanning the plurality of first hierarchy sets and selecting at least one of the first hierarchy sets for activation;

a second hierarchy address selection circuit scanning the second hierarchy sets; and

a data supply circuit writing a plurality of data into a designated second hierarchy set according to the scanning sequence of the second hierarchy address selection circuit.

2. The multi-dimensional data registration integrated circuit for driving array-arrangement devices of claim 1, wherein the first hierarchy address selection circuit comprises a level shift register circuit outputting a plurality of first hierarchy address selection signals for selecting the plurality of first hierarchy sets.

3. The multi-dimensional data registration integrated circuit for driving array-arrangement devices of claim 1, wherein the second hierarchy address selection circuit comprises a level shift register circuit outputting a plurality of second hierarchy address selection signals for selecting the plurality of second hierarchy sets.

4. The multi-dimensional data registration integrated circuit for driving array-arrangement devices of claim 1, wherein the array-arrangement devices are a plurality of thermal-optical switches.

5. The multi-dimensional data registration integrated circuit for driving array-arrangement devices of claim 1, wherein the array-arrangement devices are thermal resistors for controlling a plurality of nozzles of a printhead chip.

6. The multi-dimensional data registration integrated circuit for driving array-arrangement devices of claim 1, wherein each of the second hierarchy sets is further divided into a plurality of third hierarchy sets, and the second hierarchy address selection circuit scans the third hierarchy sets for selecting at least one of the third hierarchy sets for activation.

7. The multi-dimensional data registration integrated circuit for driving array-arrangement devices of claim 6, further comprising a third hierarchy address selection circuit outputting a plurality of third hierarchy address selection signals for scanning and selecting the plurality of second hierarchy sets.

8. The multi-dimensional data registration integrated circuit for driving array-arrangement devices of claim 1, wherein the first hierarchy address selection circuit comprises asymmetric MOSFET devices or CMOSFET devices.

9. The multi-dimensional data registration integrated circuit for driving array-arrangement devices of claim 1, wherein the second hierarchy address selection circuit comprises asymmetric MOSFET devices or CMOSFET devices.

10. The multi-dimensional data registration integrated circuit for driving array-arrangement devices of claim 1, wherein the array-arrangement devices are a plurality of printheads.