MULTI-DIMENSIONAL DATA REGISTRATION INTEGRATED CIRCUIT FOR DRIVING ARRAY-ARRANGEMENT DEVICES
First Claim
1. A multi-dimensional data registration integrated circuit for driving array-arrangement devices divided into a plurality of first hierarchy sets, each of which comprises a plurality of second hierarchy sets, comprising:
- a first hierarchy address selection circuit scanning the plurality of first hierarchy sets and selecting at least one of the first hierarchy sets for activation;
a second hierarchy address selection circuit scanning the second hierarchy sets; and
a data supply circuit writing a plurality of data into a designated second hierarchy set according to the scanning sequence of the second hierarchy address selection circuit.
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Accused Products
Abstract
A multi-dimensional data registration integrated circuit is configured for driving array-arrangement devices. The array-arrangement devices comprise a plurality of first hierarchy sets, each which comprises a plurality of second hierarchy sets. The multi-dimensional data registration integrated circuit comprises a first hierarchy address selection circuit, a second hierarchy address selection circuit and a data supply circuit. The first hierarchy address selection circuit scans the first hierarchy sets, and selects a unit of the first hierarchy sets to activate it. The second hierarchy address selection circuit scans the second hierarchy sets. The data supply circuit writes a plurality of data into each designated unit of the second hierarchy sets according to the scanning sequence of the second hierarchy address selection circuit.
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Citations
10 Claims
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1. A multi-dimensional data registration integrated circuit for driving array-arrangement devices divided into a plurality of first hierarchy sets, each of which comprises a plurality of second hierarchy sets, comprising:
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a first hierarchy address selection circuit scanning the plurality of first hierarchy sets and selecting at least one of the first hierarchy sets for activation; a second hierarchy address selection circuit scanning the second hierarchy sets; and a data supply circuit writing a plurality of data into a designated second hierarchy set according to the scanning sequence of the second hierarchy address selection circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification