Wafer level edge stacking

• US 20090316378A1
• Filed: 06/15/2009
• Published: 12/24/2009
• Est. Priority Date: 06/16/2008
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera Research LLC (Adeia Inc.)
• Inventors: Kriman, Moshe, Mirkarimi, Laura, Mohammed, Ilyas, Haba, Belgacem
• Granted Patent: US 8,680,662 B2
• Time in Patent Office: Days
• US Class Current: 361/808
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0235 Shape of the redistribution layers
• CPC Class Codes: H01L 2224/02351 comprising interlocking features
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/06155 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08148 the bonding area connecting to a bonding area protruding from the surface of the body
• CPC Class Codes: H01L 2224/09181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16148 the bump connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/24105 Connecting bonding areas at different heights
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/24146 the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
• CPC Class Codes: H01L 2224/244 Connecting portions
• CPC Class Codes: H01L 2224/245 : Material
• CPC Class Codes: H01L 2224/25105 : Connecting at different heights
• CPC Class Codes: H01L 2224/25174 : Stacked arrangements
• CPC Class Codes: H01L 2224/2518 : being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/80001 : by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/808 : Bonding techniques
• CPC Class Codes: H01L 2224/82365 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/82815 : Reflow soldering
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/92144 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06551 : Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06558 : the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1064 : Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01067 : Holmium [Ho]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: Y10T 29/49144 : by metal fusion

Abstract

A microelectronic assembly can include a first microelectronic device and a second microelectronic device. Each microelectronic device has a die structure including at least one semiconductor die and each of the microelectronic devices has a first surface, a second surface remote from the first surface and at least one edge surface extending at angles other than a right angle away from the first and second surfaces. At least one electrically conductive element extends along the first surface onto at least one of the edge surfaces and onto the second surface. At least one conductive element of the first microelectronic device can be conductively bonded to the at least one conductive element of the second microelectronic device to provide an electrically conductive path therebetween.

Claims

1. A microelectronic assembly, comprising:

a first microelectronic device and a second microelectronic device, each of the microelectronic devices including a die structure including at least one semiconductor die and each of the microelectronic devices having a first surface, a second surface remote from the first surface and at least one edge surface extending at angles other than a right angle away from the first and second surfaces, and at least one electrically conductive element extending along the first surface onto at least one of the edge surfaces and onto the second surface, the at least one conductive element of the first microelectronic device being conductively bonded to the at least one conductive element of the second microelectronic device to provide an electrically conductive path therebetween.

2. A microelectronic assembly as claimed in claim 1, wherein the electrically conductive elements of each microelectronic device include first elements formed by plating onto one of the first and second surfaces and second elements formed by plating onto another one of the first and second surfaces and the at least one edge surface, wherein the second elements are plated onto portions of the first elements.

3. A microelectronic assembly as claimed in claim 2, wherein the second elements extend along the portions of the first elements on which the second elements are plated.

4. A microelectronic assembly as claimed in claim 2, wherein the second elements extend along edges of the first elements.

5. A microelectronic assembly as claimed in claim 1, wherein the conductive elements are bonded using a fusible metal.

6. A microelectronic assembly as claimed in claim 1, wherein the conductive elements are bonded using conductive paste.

7. A microelectronic assembly as claimed in claim 1, wherein one of the first and second surfaces of the first microelectronic device confronts one of the first and second surfaces of the second microelectronic device and portions of the conductive elements exposed at the confronting surfaces are bonded together.

8. A microelectronic assembly as claimed in claim 7, wherein the conductive elements include conductive pads exposed at at least one of the first or second surfaces of each microelectronic device, the conductive pads being bonded together.

9. A microelectronic assembly as claimed in claim 7, wherein the conductive elements include traces and conductive pads, wherein the at least one conductive pad is disposed a spaced distance from the at least one edge surface.

10. A microelectronic assembly as claimed in claim 7, wherein the conductive element of each microelectronic device includes a conductive pad proximate the at least one edge surface.

11. A microelectronic assembly as claimed in claim 10, wherein the conductive pad extends to the at least one edge surface.

12. A microelectronic assembly as claimed in claim 1, wherein at least one of the die structures includes a plurality of semiconductor dies.

13. A microelectronic assembly as claimed in claim 12, wherein the bond pad-bearing surfaces of at least two of the semiconductor dies included in the at least one die structure face in the same direction.

14. A microelectronic assembly as claimed in claim 12, wherein the bond pad-bearing surfaces of at least two of the semiconductor dies included in the at least one die structure face in different directions.

15. A microelectronic assembly as claimed in claim 1, wherein the edge surface extends at an angle of between 50 degrees and 89 degrees with respect to at least one of the first and second surfaces.

16. A microelectronic assembly as claimed in claim 1, wherein the first and second microelectronic devices are stacked in a vertical direction and the at least one edge surfaces of the first and second microelectronic devices are offset from each other in a direction away from the vertical direction.

17. A microelectronic assembly as claimed in claim 1, wherein the first surfaces of the first and second microelectronic devices extend in lateral directions and have first dimensions in the lateral directions, wherein the lateral dimensions of the first surfaces of the first and second microelectronic devices are different.

18. A microelectronic assembly, comprising:

a first microelectronic device and a second microelectronic device, each of the microelectronic devices including a die structure including at least one semiconductor die and each of the microelectronic devices having a first surface, a second surface remote from the first surface and at least one edge surface extending away from the first surface, and at least one electrically conductive element extending along the first surface and onto at least one of the edge surfaces, the at least one conductive element of the first microelectronic device being conductively bonded to the at least one conductive element of the second microelectronic device to provide an electrically conductive path therebetween.

19. A microelectronic assembly as claimed in claim 18, wherein the at least one edge surface extends at an angle other than a right angle away from the first and second surfaces.

20. A microelectronic assembly as claimed in claim 18, wherein at least edge portions of the electrically conductive elements exposed at the at least one edge surfaces are conductively bonded to provide the electrically conductive path.

21. A microelectronic assembly as claimed in claim 20, wherein the at least edge portions of the conductive elements are bonded using a fusible metal.

22. A microelectronic assembly as claimed in claim 20, wherein the at least edge portions of the conductive elements are bonded using conductive paste.

23. A method of fabricating a stacked microelectronic assembly, comprising:

arranging a major surface of a first microelectronic device to confront a major surface of a second microelectronic device and conductively bonding an electrically conductive element exposed at the major surface of a first microelectronic device with an electrically conductive element exposed at the major surface of the second microelectronic device to provide an electrically conductive path therebetween, wherein each of the microelectronic devices includes a die structure including at least one semiconductor die and each of the microelectronic devices has a first major surface, a second major surface remote from the first surface, at least one edge surface and at least one electrically conductive element extending along the first surface onto at least one of the edge surfaces and onto the second major surface.

24. A method of fabricating a stacked microelectronic assembly, comprising:

forming a stack including a first microelectronic device with a second microelectronic device, each of the microelectronic devices including a die structure including at least one semiconductor die and each of the microelectronic devices having a first surface, a second surface remote from the first surface and at least one edge surface extending away from the first surface, and at least one electrically conductive element extending along the first surface and onto at least one of the edge surfaces; and

conductively bonding portions of the conductive elements exposed at the edge surfaces to provide an electrically conductive path therebetween.

25. A method as claimed in claim 24, wherein the first microelectronic device is disposed above the second microelectronic device, and the step of bonding is performed by heating a fusible metal proximate the conductive element exposed at the at least one edge surface of the first microelectronic device such that the fusible metal flows onto the conductive element exposed at the at least one edge surface of the second microelectronic device.

26. A method as claimed in claim 25, wherein the fusible metal bridges a gap between the conductive elements of the first and second microelectronic devices.

27. A method as claimed in claim 24, wherein the first microelectronic device is disposed above the second microelectronic device, and the step of bonding is performed by dispensing a flowable conductive material onto the conductive element exposed at the at least one edge surface of the first microelectronic device such that the conductive material flows onto the conductive element exposed at the at least one edge surface of the second microelectronic device.