Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array

• US 20090316487A1
• Filed: 06/22/2009
• Published: 12/24/2009
• Est. Priority Date: 06/20/2008
• Status: Active Grant

• Current Assignee: Aplus Flash Technology, Inc.
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Lee, Peter Wung, Tsao, Hsing-Ya, Hsu, Fu-Chang
• Granted Patent: US 8,289,775 B2
• Time in Patent Office: Days
• US Class Current: 365/185.220
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/565 Multilevel memory comprising elements in triple well structure

Abstract

An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing sub-threshold leakage current through unselected nonvolatile memory cells. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing sub-threshold leakage current through unselected nonvolatile memory cells.

Claims

1. A nonvolatile memory device comprising:

an array of nonvolatile memory cells arranged in rows and columns, such that the nonvolatile memory cells located on each column are connected in groups such that the drains of each of the nonvolatile memory cells are connected to communicate with a local bit line associated with each column, the nonvolatile memory cells on each row have their gates commonly connected to a word line, and the nonvolatile memory cells one two adjacent rows have their sources commonly connected to a source line, wherein the array of nonvolatile memory cells is partitioned into sectors, where each sector is placed in an isolation well of a first impurity type and each sector of the array of the nonvolatile memory cells is divided into blocks and each block is divided into pages, and each page includes one row of the nonvolatile memory cells within each sector of each block connected to a word line;

a plurality of peripheral circuits connected to the word lines, bit lines, and sources lines to provide biasing voltages for reading, programming, erasing, and verifying selected nonvolatile memory cells, such that the biasing voltages do not exceed a drain to source breakdown voltage of the peripheral circuits and have word line of unselected cells set to a word line read inhibit voltage level during a read operation and to a program inhibit voltage level during a program operation and source lines of unselected cells are set to a source line inhibit voltage level to minimize a sub-threshold leakage current through each of the unselected nonvolatile memory cells.

2. The nonvolatile memory device of claim 1 wherein the peripheral circuit comprises a plurality of transistors, such that the drain to source breakdown voltage is less than from approximately 8.0V to 10.0V.

3. The nonvolatile memory device of claim 1 wherein the groups of nonvolatile memory cells are connected into a NOR configuration or a NAND configuration.

4. The nonvolatile memory device of claim 1 wherein the groups of nonvolatile memory cells comprise charge storing floating gate transistors or charge trapping SONOS transistors.

5. The nonvolatile memory device of claim 1 wherein the peripheral circuit comprises:

a row decoder for selecting rows of the nonvolatile memory cells and the row decoder comprises;

a first block selector that activates when a block address indicates that a block is selected,

a word line selector circuit connected to the first block selector circuit, which based on a row address provides the word lines with word line operational voltage levels necessary for biasing the control gates of the nonvolatile memory cells for reading, programming, verifying, and erasing;

a first voltage level shifter connected to the first block selector circuit for shifting a voltage level of a block select signal to activate pass gates to transfer the operational voltage levels to the word lines of the selected block for biasing the control gates of the nonvolatile memory cells of the block for reading, programming, verifying, and erasing the selected nonvolatile memory cells.

6. The nonvolatile memory device of claim 5 wherein the peripheral circuit comprises:

a source decoder circuit connected to each source line within each block to transfer necessary source line biasing voltage for reading,

programming, verifying, and erasing selected nonvolatile memory cells wherein the source decoder comprises;

a second block selector circuit which activates for the selection of the block being addressed, and

a source voltage level shifter connected to the block selector circuit to shift a voltage level of the block selector signals for activating pass transistors to transfer source line operational voltages to the source lines connected to the sources of the nonvolatile memory cells of the selected block for reading, programming, verifying, and erasing the selected nonvolatile memory cells.

7. The nonvolatile memory device of claim 6 wherein the peripheral circuit comprises:

a column decoder in communication with a local bit line for providing biasing voltages for reading, programming, verifying, and erasing selected nonvolatile memory cells.

8. The nonvolatile memory device of claim 1 wherein the row decoder, source decoder, and column decoder provide inhibit biasing voltage levels to all the non-selected nonvolatile memory cells to minimize disturbances and sub-threshold leakage current in unselected nonvolatile cells resulting from the reading, programming, verifying, and erasing selected nonvolatile memory cells.

9. The nonvolatile memory device of claim 8 wherein for reading a selected page of the array of nonvolatile memory cells:

the row decoder transfers;

a word line read biasing voltage level to the word line of the selected nonvolatile memory cells;

the word line read inhibit voltage level to the word lines of the unselected nonvolatile memory cells to minimize the sub-threshold leakage current through each of the unselected nonvolatile memory cells;

the column decoder transfers;

a first bit line read biasing voltage to the drains of the selected nonvolatile memory cells; and

the source decoder transfers;

source line read biasing voltage to the source lines of the selected nonvolatile memory cells and transfers a source line read inhibit voltage to the source lines of the unselected nonvolatile memory cells to minimize the sub-threshold leakage current through each of the unselected nonvolatile memory cells.

10. The nonvolatile memory device of claim 9 wherein the voltage level of the word line read biasing voltage is approximately the voltage level of the power supply voltage source for a single level cell program for slow read of the selected nonvolatile memory cells

11. The nonvolatile memory device of claim 9 wherein the word line read biasing voltage is a high read select voltage for a multiple level cell program for slow reading of the selected nonvolatile memory cells.

12. The nonvolatile memory device of claim 9 wherein the word line read biasing voltage is a high read select voltage for the single level cell program and the multiple level cell program for fast reading of the selected nonvolatile memory cells.

13. The nonvolatile memory device of claim 10 wherein the voltage level of the power supply voltage source is +1.8V or +3.0V and the high read select voltage is approximately +5.0V.

14. The nonvolatile memory device of claim 9 wherein the voltage level of the first bit line read biasing voltage is approximately +1.0V and the source line read inhibit voltage level is approximately +1.0V.

15. The nonvolatile memory device of claim 8 wherein for programming a selected page of the array of nonvolatile memory cells:

the row decoder transfers;

a very high negative program voltage to the word line of the selected nonvolatile memory cells, and

a positive program inhibit voltage to the word lines of the unselected word lines is the selected block and the unselected blocks of the array of nonvolatile memory cells;

the column decoder transfers;

a bit line high program select voltage to the bit lines and thus to the drains of the selected nonvolatile memory cells; and

the source line decoder transfers;

the ground reference voltage level to the source lines connected to the selected nonvolatile voltage cells; and

a second source line program inhibit voltage to the source lines of the unselected nonvolatile memory cells.

16. The nonvolatile memory device of claim 15 wherein the voltage level of the very high negative program voltage is less than the breakdown voltage level of transistors forming the row decoder.

18. The nonvolatile memory device of claim 15 wherein the voltage level of the negative word line program inhibit biasing voltage is approximately −

2.0V.

19. The nonvolatile memory device of claim 15 wherein the high program select voltage is approximately +5.0V.

20. The nonvolatile memory device of claim 15 wherein second source line program inhibit voltage is from approximately +1.5V to approximately +1.8V.

21. The nonvolatile memory device of claim 8 wherein for verifying a page program:

the row decoder transfers;

a voltage level of an upper boundary of a programmed threshold voltage level to the word line of the selected nonvolatile memory cells for the single level cell programming and iteratively set to a the upper boundaries of a first threshold voltage level, a second threshold voltage level and a third threshold voltage level, and

the word line inhibit biasing voltage to the word lines of the unselected nonvolatile memory cells;

the column decoder transfers;

a second bit line read biasing voltage to the drains of the selected nonvolatile memory cells to pre-charge the bit line connected to the drains of the selected nonvolatile memory cells to the second bit line read biasing voltage, wherein the pre-charged level of the second bit line read biasing voltage level is discharged to approximately 0.0V if the memory cell has not been successfully erased to the erased threshold voltage level that is lower than the lower boundary of the erased threshold voltage level and if the selected nonvolatile memory cells are erased, the pre-charged level of the second bit line read biasing voltage level will be maintained when the threshold voltage of the erased nonvolatile memory cells is greater than the erased threshold voltage level;

the source decoder transfers;

the ground reference voltage level to the source lines of the selected nonvolatile memory cells, and

the first source line read inhibit voltage to the source lines of the unselected nonvolatile memory cells.

22. The nonvolatile memory device of claim 21 wherein the upper boundary of the programmed threshold voltage level is approximately +1.5V for the single level cell programming.

23. The nonvolatile memory device of claim 21 wherein the upper boundaries of a first threshold voltage level, a second threshold voltage level and a third threshold voltage level are respectively +1.5V, +3.0V, and +4.5V for the multiple level cell programming.

24. The nonvolatile memory device of claim 21 wherein the voltage level of the second bit line read biasing voltage is the voltage level of the power supply voltage source less a threshold voltage level of an NMOS transistor, wherein power supply voltage source is +1.8V or +2.3V.

25. The nonvolatile memory device of claim 21 wherein the voltage level of the second source line read inhibit voltage is approximately +1.0V.

26. The nonvolatile memory device of claim 8 for erasing a selected page, a selected block or a selected sector of the array of nonvolatile memory cells:

a very high negative erase voltage is applied to an isolation well of the first impurity type into which the sector of nonvolatile memory cells is formed.

the row decoder of selected blocks transfers;

a very high positive erase voltage to the word line of the selected nonvolatile memory cells,

and the ground reference voltage level to the word lines of the unselected nonvolatile memory cells of the selected block;

The row decoders of the unselected blocks of nonvolatile memory cells;

disconnect the word lines of the unselected nonvolatile memory cells so that the very high negative erase voltage is coupled from an isolation well of the first impurity type to the word lines of the unselected nonvolatile memory cells in unselected blocks; and

The source line decoder transfers;

the very high negative erase voltage to the selected and unselected source lines.

27. The nonvolatile memory device of claim 26wherein the voltage levels of the very high positive erase voltage and the very high negative erase voltage is approximately the breakdown voltage level of transistors forming the row decoder, column decoder, and the source line decoder.

28. The nonvolatile memory device of claim 26 wherein the voltage level of the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the voltage level of the very high negative erase voltage is from approximately −

10.0V to approximately −

8.0V.

29. The nonvolatile memory device of claim 8 wherein for verifying erasing of a selected page, a selected block or a selected page of the array of nonvolatile memory cells:

the row decoder transfers;

a voltage level of a lower boundary of an erased threshold voltage level to the word line of the selected nonvolatile memory cells, and

word line read inhibit biasing voltage to the word lines of the word lines of the unselected nonvolatile memory cells to minimize a sub-threshold leakage current through each of the unselected nonvolatile memory cells;

the column decoder transfers;

the second bit line read biasing voltage to the drains of the selected nonvolatile memory cells to pre-charge the bit line connected to the drains of the selected nonvolatile memory cells to the second bit line read biasing voltage, wherein the pre-charged level of the second bit line read biasing voltage level is discharged to approximately 0.0V if the memory cell has not been successfully erased to the erased threshold voltage level that is lower than the lower boundary of the erased threshold voltage level and if the selected nonvolatile memory cells are erased, the pre-charged level of the second bit line read biasing voltage level will be maintained when the threshold voltage of the erased nonvolatile memory cells is greater than the erased threshold voltage level.

the source line decoder transfers;

the ground reference voltage level to the source lines of the selected nonvolatile memory cells, and

the source line read inhibit voltage to the source lines of the unselected nonvolatile memory cells.

31. The nonvolatile memory device of claim 18 wherein the voltage level of the second bit line read biasing voltage is the voltage level of the power supply voltage source less a threshold voltage level of an NMOS transistor, wherein power supply voltage source is +1.8V or +2.3V.

32. The nonvolatile memory device of claim 18 wherein the voltage level of the source line read inhibit voltage is approximately +1.0V.

33. A method for operating an array of nonvolatile memory cells comprise the steps of:

slow reading a selected page of the array of nonvolatile memory cells by the steps of;

applying a first word line read biasing voltage to the word line of the selected nonvolatile memory cells for a single level cell program,

applying a second word line read biasing voltage level to the word line of the selected nonvolatile memory cells for a multiple level cell program,

applying a first word line read inhibit voltage level to the word lines of the unselected nonvolatile memory cells for a single level cell program to minimize sub-threshold leakage currents in the unselected nonvolatile memory cells having the single level cell program,

applying a second word line read inhibit voltage level to the word lines of the unselected nonvolatile memory cells for a multiple level cell program to minimize sub-threshold leakage currents in the unselected nonvolatile memory cells having the multiple level cell program,

applying a first bit line read biasing voltage to bit lines of the array of the selected nonvolatile memory cells,

applying a source line read biasing voltage to the selected source lines of the array of the selected nonvolatile memory cells, and

applying a source line read inhibit voltage to the unselected source lines of the unselected nonvolatile memory cells to shift the threshold biasing voltages of the unselected nonvolatile memory cells to minimize the sub-threshold leakage current in the unselected nonvolatile memory cells.

17. The nonvolatile memory device of claim 34 wherein the voltage level of the high negative program voltage −

10.0V to approximately −

8.0V.

30. The nonvolatile memory device of claim 81 wherein the lower boundary of an erased threshold voltage level is approximately 6.0V for the single level cell program and a multiple level cell programming.

34. The method for operating an array of nonvolatile memory cells of claim 33 wherein the first word line read biasing voltage is approximately the voltage level of the power supply voltage source.

35. The method for operating an array of nonvolatile memory cells of claim 33 wherein the voltage level of the power supply voltage source is +1.8V or +3.0V.

36. The method for operating an array of nonvolatile memory cells of claim 33 wherein the first read inhibit voltage level is approximately −

2.0V.

37. The method for operating an array of nonvolatile memory cells of claim 33 wherein the second read inhibit voltage level is approximately the ground reference voltage level.

38. The method for operating an array of nonvolatile memory cells of claim 33 wherein the voltage level of the second word line read biasing voltage is approximately +5.0V.

39. The method for operating an array of nonvolatile memory cells of claim 33 wherein the bit line read biasing voltage is approximately +1.0V.

40. The method for operating an array of nonvolatile memory cells of claim 33 wherein the source line read biasing voltage is approximately the ground reference voltage level

41. The method for operating an array of nonvolatile memory cells of claim 33 wherein the voltage level of the source line read inhibit voltage is approximately +1.0V.

42. The method for operating an array of nonvolatile memory cells of claim 33 further comprising:

fast reading a selected page of the array of nonvolatile memory cells by the steps of;

applying the second word line read biasing voltage level to the word line of the selected nonvolatile memory cells for the single level cell program and for the multiple level cell program,

applying the second word line read inhibit voltage level to the word lines of the unselected nonvolatile memory cells to minimize sub-threshold leakage currents in the unselected nonvolatile memory cells having the single level cell program or the multiple level cell program,

applying the first bit line read biasing voltage to bit lines of the array of the selected nonvolatile memory cells,

applying the source line read biasing voltage to the selected source lines of the array of the selected nonvolatile memory cells, and

applying the source line read inhibit voltage to the unselected source lines of the unselected nonvolatile memory cells to shift the threshold biasing voltages of the unselected nonvolatile memory cells to minimize the sub-threshold leakage current in the unselected nonvolatile memory cells.

43. The method for operating an array of nonvolatile memory cells of claim 42 wherein the first word line read biasing voltage is approximately the voltage level of the power supply voltage source.

44. The method for operating an array of nonvolatile memory cells of claim 42 wherein the voltage level of the power supply voltage source is +1.8V or +3.0V.

45. The method for operating an array of nonvolatile memory cells of claim 42 wherein the first read inhibit voltage level is approximately −

2.0V.

46. The method for operating an array of nonvolatile memory cells of claim 42 wherein the second read inhibit voltage level is approximately the ground reference voltage level.

47. The method for operating an array of nonvolatile memory cells of claim 42 wherein the voltage level of the second word line read biasing voltage is approximately +5.0V.

48. The method for operating an array of nonvolatile memory cells of claim 42 wherein the bit line read biasing voltage is approximately +1.0V.

49. The method for operating an array of nonvolatile memory cells of claim 42 wherein the source line read biasing voltage is approximately the ground reference voltage level

50. The method for operating an array of nonvolatile memory cells of claim 42 wherein the voltage level of the source line read inhibit voltage is approximately +1.0V.

51. The method for operating an array of nonvolatile memory cells of claim 42 wherein the first word line read biasing voltage is approximately the voltage level of the power supply voltage source.

52. The method for operating an array of nonvolatile memory cells of claim 51 wherein the voltage level of the power supply voltage source is +1.8V or +3.0V.

53. The method for operating an array of nonvolatile memory cells of claim 57 wherein the voltage level of the second word line read biasing voltage is approximately +5.0V.

54. The method for operating an array of nonvolatile memory cells of claim 42 wherein the bit line read biasing voltage is approximately +1.0V.

55. The method for operating an array of nonvolatile memory cells of claim 42 wherein the source line read biasing voltage is approximately the ground reference voltage level

56. The method for operating an array of nonvolatile memory cells of claim 42 wherein the voltage level of the source line read inhibit voltage is approximately +1.0V.

57. The method for operating an array of nonvolatile memory cells of claim 33 further comprising the step of;

programming a selected page of the array of nonvolatile memory cells by the steps of;

applying a very high negative word line program voltage to the word line of the selected nonvolatile memory cells;

applying a positive program word line inhibit voltage to the word lines of the unselected word lines in a selected block and unselected blocks of the array of nonvolatile memory cells;

applying a high program select voltage to the bit lines and thus to the drains of the selected nonvolatile memory cells;

applying a source line program biasing voltage to the source lines connected to the selected nonvolatile voltage cells; and

applying a source line program inhibit voltage to the source lines of the unselected nonvolatile memory cells.

58. The method for operating an array of nonvolatile memory cells of claim 57 wherein the voltage level of the very high negative program voltage is approximately the breakdown voltage level of transistors forming the row decoder.

59. The method for operating an array of nonvolatile memory cells of claim 57 wherein the voltage level of the high negative word line program voltage is from approximately −

10.0V to approximately −

8.0V.

60. The method for operating an array of nonvolatile memory cells of claim 57 wherein the voltage level of the negative word line program inhibit voltage is approximately −

2.0V.

61. The method for operating an array of nonvolatile memory cells of claim 57 wherein the high bit line program select voltage is approximately +5.0V for single level cell program.

62. The method for operating an array of nonvolatile memory cells of claim 57 wherein the high bit line program select voltage is approximately +4.0V, approximately +5.0V or approximately +6.0V dependent on a datum to be programmed for multiple level cell program.

63. The method for operating an array of nonvolatile memory cells of claim 57 wherein the source line program biasing voltage is approximately the ground reference voltage level.

64. The method for operating an array of nonvolatile memory cells of claim 57 wherein the source line program inhibit voltage is from approximately +1.5V to approximately +1.8V.

65. The method for operating an array of nonvolatile memory cells of claim 33 further comprising the step of;

verifying a page programming of a selected page of the array of nonvolatile memory cells by the steps of;

applying the voltage level of an upper boundary of a programmed threshold voltage level to the word line of the selected nonvolatile memory cells for the single level cell programming;

iteratively applying the upper boundaries of a first threshold voltage level, a second threshold voltage level and a third threshold voltage level to the word line of the selected nonvolatile memory cells for the multiple level cell programming.

applying the word line read inhibit voltage to the word lines of the word lines of the unselected nonvolatile memory cells;

applying a second bit line read biasing voltage to the drains of the selected nonvolatile memory cells to pre-charge the bit line connected to the drains of the selected nonvolatile memory cells to the second bit line read biasing voltage, wherein the pre-charged level of the second bit line read biasing voltage level is discharged to approximately 0.0V if the memory cell has not been successfully erased to the erased threshold voltage level that is lower than the lower boundary of the erased threshold voltage level and if the selected nonvolatile memory cells are erased, the pre-charged level of the second bit line read biasing voltage level will be maintained when the threshold voltage of the erased nonvolatile memory cells is greater than the erased threshold voltage level;

applying the source line read biasing voltage to the source lines of the selected nonvolatile memory cells; and

applying a source line read inhibit voltage to the source lines of the unselected nonvolatile memory cells.

66. The method for operating an array of nonvolatile memory cells of claim 65 wherein the upper boundary of a programmed threshold voltage level is approximately +1.5V for the single level cell programming.

67. The method for operating an array of nonvolatile memory cells of claim 65 wherein the upper boundaries of a first threshold voltage level, a second threshold voltage level and a third threshold voltage level are respectively +1.5V, +3.0V, and +4.5V for the multiple level cell programming.

68. The method for operating an array of nonvolatile memory cells of claim 65 wherein the word line read inhibit biasing voltage is −

2.0V.

69. The method for operating an array of nonvolatile memory cells of claim 65 wherein the voltage level of the bit line read biasing voltage is approximately +5.0V.

70. The method for operating an array of nonvolatile memory cells of claim 65 wherein the voltage level of the source line read inhibit voltage is approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor wherein the voltage level of the power supply voltage source is +1.8V or +3.0V.

71. The method for operating an array of nonvolatile memory cells of claim 65 wherein the voltage level of the source line read inhibit voltage is approximately +1.0V.

72. The method for operating an array of nonvolatile memory cells of claim 65 wherein the source line read biasing voltage is approximately the ground reference voltage level

73. The method for operating an array of nonvolatile memory cells of claim 65 wherein the voltage level of the source line read inhibit voltage is approximately +1.0V.

74. The method for operating an array of nonvolatile memory cells of claim 33 further comprising the steps of:

erasing a selected page, selected block, or a selected sector of the array of nonvolatile memory cells by the steps of;

applying a very high negative erase voltage to an isolation well of the first impurity type

applying a very high positive erase voltage to the word line of the selected nonvolatile memory cells;

applying a word line erase inhibit voltage level to word lines of unselected nonvolatile memory cells of the selected block;

disconnecting the word lines of the unselected nonvolatile memory cells so that the very high negative erase voltage is coupled from the isolation well of the first impurity type to the word lines of the unselected nonvolatile memory cells in unselected blocks;

applying the very high negative erase voltage to selected and unselected source lines;

75. The method for operating an array of nonvolatile memory cells of claim 74 wherein the voltage levels of the very high positive erase voltage and the very high negative erase voltage are approximately the breakdown voltage level of transistors forming peripheral circuitry of the array of nonvolatile memory cells.

76. The method for operating an array of nonvolatile memory cells of claim 74 wherein the voltage level of the very high positive erase voltage is from approximately +8.0V to approximately +10.0V and the voltage level of the very high negative erase voltage is −

10.0V to approximately −

8.0V.

77. The method for operating an array of nonvolatile memory cells of claim 74 where in the word line erase inhibit voltage level is approximately the ground reference voltage level.

78. The method for operating an array of nonvolatile memory cells of claim 33 further comprising the step of:

verifying a page erase of the selected page, the selected block, or the selected sector of the array of nonvolatile memory cells by the steps of;

applying a voltage level of a lower boundary of an erased threshold voltage level to the word line of the selected nonvolatile memory cells;

applying the ground reference voltage level to the word lines of the word lines of the unselected nonvolatile memory cells;

applying the second bit line read biasing voltage to the drains of the selected nonvolatile memory cells to pre-charge the bit line connected to the drains of the selected nonvolatile memory cells to the second bit line read biasing voltage, wherein the pre-charged level of the second bit line read biasing voltage level is discharged to approximately 0.0V if the memory cell has not been successfully erased to the erased threshold voltage level that is lower than the lower boundary of the erased threshold voltage level and if the selected nonvolatile memory cells are erased, the pre-charged level of the second bit line read biasing voltage level will be maintained when the threshold voltage of the erased nonvolatile memory cells is greater than the erased threshold voltage level;

applying the source line read biasing voltage to the source lines of the selected nonvolatile memory cells; and

applying a second source line read inhibit voltage to the source lines of the unselected nonvolatile memory cells.

79. The method for operating an array of nonvolatile memory cells of claim 78 wherein the lower boundary of an erased threshold voltage level is approximately 6.0V for the single level cell program and the multiple level cell programming.

80. The method for operating an array of nonvolatile memory cells of claim 78 wherein the voltage level of the second bit line read biasing voltage is approximately the voltage level of the power supply voltage source less a threshold voltage of an NMOS transistor.

81. The method for operating an array of nonvolatile memory cells of claim 80 wherein the voltage level of the power supply voltage source is +1.8V or +2.3V.

82. The method for operating an array of nonvolatile memory cells of claim 78 wherein the lower boundary of an erased threshold voltage level is approximately +6.0V.

83. The method for operating an array of nonvolatile memory cells of claim 78 wherein the source line read biasing voltage is approximately the ground reference voltage level

84. The method for operating an array of nonvolatile memory cells of claim 78 wherein the voltage level of the second source line read inhibit voltage is approximately +2.0V.

85. A method for operating of a charge retaining charge retaining nonvolatile memory device comprising;

inhibiting sub-threshold leakage current in unselected charge retaining nonvolatile memory devices during a read operation by the steps of;

applying a bit line read biasing voltage to the selected bit lines voltage;

applying a source line inhibit voltage approximately equal to the read biasing voltage to the unselected source lines connected to charge retaining nonvolatile memory cells connected to the selected bit lines; and

applying a word line read inhibit voltage to the unselected word lines.

inhibiting sub-threshold leakage current in unselected charge retaining nonvolatile memory cells connected to selected bit lines during a program operation by the steps of;

applying a negative word program inhibit voltage to the word line of the unselected charge retaining nonvolatile memory cell.

inhibiting leakage current in unselected charge retaining nonvolatile memory cells connected to unselected bit lines by steps of;

applying a word line program inhibit voltage to the unselected word lines.

applying a source line program inhibit voltage to the source lines of the unselected charge retaining nonvolatile memory cells connected to the unselected bit lines.

86. The method of claim 85 wherein the bit line read biasing voltage level and the source line read inhibit voltage level is approximately +1.0V.

87. The method of claim 85 wherein the negative word line read inhibit voltage is approximately −

2.0V.

88. The method of claim 85 wherein the negative word line program inhibit voltage is approximately −

2.0V.

89. The method of claim 85 wherein the source line program inhibit voltage is from approximately +1.5V to approximately +1.8V.