DYNAMIC PASS VOLTAGE
First Claim
Patent Images
1. A method for operating a memory device, comprising:
- applying one or more sensing voltages to one or more selected access lines for sensing one or more selected memory cells; and
applying a dynamic pass voltage to one or more unselected access lines while the one or more sensing voltages are applied.
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Abstract
The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying sensing voltages to selected access lines for sensing selected memory cells. The method also includes applying a dynamic pass voltage to unselected access lines while the sensing voltages are applied.
45 Citations
33 Claims
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1. A method for operating a memory device, comprising:
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applying one or more sensing voltages to one or more selected access lines for sensing one or more selected memory cells; and applying a dynamic pass voltage to one or more unselected access lines while the one or more sensing voltages are applied. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for operating a memory device, comprising:
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applying a sensing voltage to a selected access line for a particular time to sense a selected memory cell; and applying a negatively ramping dynamic pass voltage to a number of unselected access lines during at least a portion of the particular time to put a number of unselected memory cells in a conductive state. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method for sensing memory cells, comprising:
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applying one or more sensing voltages to an access gate of a selected memory cell; applying a dynamic pass voltage to access gates of one or more unselected memory cells coupled in series to the selected memory cell; wherein applying the dynamic pass voltage includes decreasing the dynamic pass voltage while applying the one or more sensing voltages; and wherein applying the dynamic pass voltage includes starting the dynamic pass voltage at an initial temperature compensated voltage.
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16. A memory device, comprising:
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one or more arrays of memory cells, each array including one or more strings of memory cells, each of the one or more strings coupled to a data line, and each memory cell coupled to an access line; control circuitry coupled to the one or more arrays and configured to; apply one or more sensing voltages to a selected access line to sense a selected memory cell; and apply a dynamic pass voltage to one or more unselected access lines while the one or more sensing voltages are applied. - View Dependent Claims (17, 18, 19, 20, 21)
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22. A memory device comprising:
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one or more NAND arrays of memory cells including at one or more strings of memory cells; a data line coupled to each of the one or more strings of memory cells; control circuitry coupled to the one or more NAND arrays and configured to; precharge the data line with a first voltage; apply one or more sensing voltages to an access line coupled to a selected memory cell until the data line discharges to a second voltage; apply a dynamic pass voltage to one or more access lines coupled to one or more unselected memory cells while the one or more sensing voltages are applied; and decrease the dynamic pass voltage from a first pass voltage to a second pass voltage while the data line discharges. - View Dependent Claims (23, 24, 25, 26)
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27. A memory system, comprising:
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a processor; a memory device coupled to the processor, the memory device comprising; one or more strings of memory cells coupled to one or more data lines; an access line coupled to each memory cell; and control circuitry coupled to the one or more strings of memory cells and configured to; apply one or more sensing voltages to one or more access lines corresponding to one or more selected memory cells; and apply a dynamic pass voltage to one or more access lines corresponding to one or more unselected memory cells. - View Dependent Claims (28, 29, 30, 31, 32, 33)
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Specification