METHOD OF WRITING DATA INTO SEMICONDUCTOR MEMORY AND MEMORY CONTROLLER

• US 20090316490A1
• Filed: 02/13/2008
• Published: 12/24/2009
• Est. Priority Date: 02/14/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takada, Tomoji
• Granted Patent: US 8,341,333 B2
• Time in Patent Office: Days
• US Class Current: 365/185.260
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A method of writing data into a semiconductor memory (11) in which nonvolatile memory cells (MC) each having a gate connected to a word line (WL) are connected in series, the method comprising selecting (S13) a scrambling method for the data according to a word line address for memory cells (MC) into which data is to be written, scrambling (S14) the data, and writing (S15) the scrambled data into the memory cells (MC) according to the word line address. The data is scrambled using the selected scrambling method.

Claims

1. A method of writing data into a semiconductor memory in which nonvolatile memory cells each having a gate connected to a word line are connected in series, the method comprising:

selecting a scrambling method for data according to a word line address for memory cells into which the data is to be written;

scrambling the data using the selected scrambling method; and

writing the scrambled data into the memory cells according to the word line address.

2. The method according to claim 1, wherein the word lines are grouped in units of a plurality of word lines adjacent to each other with at least one of the word lines between the adjacent word lines,

the data is permitted to be copied between memory cells connected to the word lines belonging to the same group, and

the data is prohibited from being copied between memory cells connected to the word lines belonging to different groups.

3. The method according to claim 1, wherein the word lines are grouped in units of a plurality of word lines adjacent to each other with at least one of the word lines between the adjacent word lines,

the groups are classified according to a remainder obtained by dividing the word line address M (M is a natural number greater than or equal to 2) by N (N is a natural number greater than or equal to 2),

first one of the scrambling methods is selected for the data to be written into the memory cells connected to the word lines belonging to first one of the groups, and

second one of the scrambling methods different from the first one of the scrambling methods is selected for the data to be written into the memory cells connected to the word lines belonging to second one of the groups different from the first one of the groups.

4. The method according to claim 1, wherein, seed data of the selected scrambling method is written together with the scrambled data into the memory cells with the corresponding word line address.

5. The method according to claim 1, wherein the word lines are grouped in units of a plurality of word lines adjacent to each other with at least one of the word lines between the adjacent word lines,

the selecting a scrambling method includes

determining to which one of the groups the word line address belongs, and

selecting the scrambling method according to the determined group from a table in which the scrambling methods are recorded for the groups in a one-to-one correspondence, and

index data given to each of the groups in the table is written together with the scrambled data into the memory cells with the corresponding word line address.

6. The method according to claim 1, wherein each of the memory cells has a stacked gate which includes a charge storage layer formed on a semiconductor substrate with a gate insulating film interposed therebetween and a control gate formed on the charge storage layer with an inter-gate insulating film interposed therebetween and connected to any one of the word lines.

7. A method of writing data into a semiconductor memory in which first nonvolatile memory cells each of whose gate is connected to a first word line and second nonvolatile memory cells each of whose gate is connected to a second word line adjacent to the first word line are connected in series, the method comprising:

scrambling first data using a first scrambling method;

writing the scrambled first data into the first memory cells;

scrambling second data using a second scrambling method differing from the first scrambling method; and

writing the scrambled second data into the second memory cells.

8. The method according to claim 7, wherein the first scrambling method is selected according to the row address of the first memory cells, and

the second scrambling method is selected according to the row address of the second memory cells.

9. The method according to claim 7, wherein seed data of the first scrambling method is written into any one of the first memory cells, and

seed data of the second scrambling method is written into any one of the second memory cells.

10. The method according to claim 7, wherein index data about the first scrambling method is written into any one of the first memory cells, and

index data about the second scrambling method is written into any one of the second memory cells.

11. The method according to claim 7, wherein each of the memory cells has a stacked gate which includes a charge storage layer formed on a semiconductor substrate with a gate insulating film interposed therebetween and a control gate formed on the charge storage layer with an inter-gate insulating film interposed therebetween and connected to any one of the word lines.

12. A memory controller which controls a semiconductor memory including a plurality of nonvolatile memory cells connected to word lines, the memory controller comprising:

an interface which is connectable to a host device and receives data to be written into the semiconductor memory from the host device;

a processor which determines a scrambling method for the data according to the word line address of the memory cells into which the data is to be written; and

a scramble circuit which scrambles the data using the scrambling method determined by the processor.

13. The controller according to claim 12, further comprising a memory which has a table holding the scrambling methods to be applied to the data to be written into the memory cells connected to each of the word lines,

wherein the processor determines the scrambling method to be used, referring to the table.

14. The controller according to claim 12, wherein the processor determines the scrambling method according to the remainder obtained by dividing the word line address by N (N is a natural number greater than or equal to 2).

15. The controller according to claim 12, wherein the data is prohibited from being copied between the memory cells holding the data to which different ones of the scrambling methods have been applied, and

the data is permitted to be copied between the memory cells holding the data to which the same one of the scrambling methods has been applied.

16. The controller according to claim 12, wherein seed data of the scrambling method determined by the processor is written together with the scrambled data into the memory cell with the corresponding word line address.

17. The controller according to claim 12, wherein index data about the scrambling method determined by the processor is written together with the scrambled data into the memory cell with the corresponding word line address.

18. The controller according to claim 12, wherein each of the memory cells has a stacked gate which includes a charge storage layer formed on a semiconductor substrate with a gate insulating film interposed therebetween and a control gate formed on the charge storage layer with an inter-gate insulating film interposed therebetween and connected to any one of the word lines.