MEMORY CELLS, MEMORY CELL ARRAYS, METHODS OF USING AND METHODS OF MAKING

• US 20090316492A1
• Filed: 09/02/2009
• Published: 12/24/2009
• Est. Priority Date: 11/29/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Granted Patent: US 8,194,451 B2
• Time in Patent Office: Days
• US Class Current: 365/189.200
• CPC Class Codes: G11C 11/4026 using bipolar transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 63/00 : Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H10N 70/231 : based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/883 : Oxides or nitrides

Abstract

A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

Claims

1. A semiconductor memory cell comprising:

a substrate having a top surface, said substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

a first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type, said first region being formed in said substrate and exposed at said top surface;

a second region having said second conductivity type, said second region being formed in said substrate, spaced apart from said first region and exposed at said top surface;

a buried layer in said substrate below said first and second regions, spaced apart from said first and second regions and having said second conductivity type;

a body region formed between said first and second regions and said buried layer, said body region having said first conductivity type;

a gate positioned between said first and second regions and above said top surface; and

a nonvolatile memory configured to store data upon transfer from said body region.

2. The semiconductor memory cell of claim 1, wherein said nonvolatile memory is further configured to restore data to said body region.

3. The semiconductor memory cell of claim 1, wherein said nonvolatile memory comprises a floating gate or trapping layer positioned in between said first and second regions, above said top surface and below said gate.

4. The semiconductor memory cell of claim 1, wherein said nonvolatile memory comprises a resistance change element connected to one of said first and second regions.

5. The semiconductor memory cell of claim 4, wherein said resistance change element comprises a phase change material.

6. The semiconductor memory cell of claim 4, wherein said resistance change element comprises a metal-oxide-metal system.

7. The semiconductor memory cell of claim 1, wherein nonvolatile memory is configured to store data upon transfer from said body region resulting from an instruction to back up said data stored in said body region.

8. The semiconductor memory cell of claim 1, wherein said transfer from said body region commences upon loss of power to said cell, wherein said cell is configured to perform a shadowing process wherein said data in said body region is loaded into and stored in said nonvolatile memory.

9. The semiconductor memory cell of claim 8, wherein said loss of power to said cell is one of unintentional power loss or intentional power loss, wherein intentional power loss is predetermined to conserve power.

10. The semiconductor memory cell of claim 8, wherein, upon restoration of power to said cell, said data in said nonvolatile memory is loaded into said body region and stored therein.

11. The semiconductor memory cell of claim 10, wherein said cell is configured to reset said nonvolatile memory to an initial state after loading said data into said body region upon said restoration of power.

12. The semiconductor memory cell of claim 11, wherein said cell is configured to reset said nonvolatile memory just prior to writing new data into said nonvolatile memory during a shadowing operation.

13. A semiconductor memory array, including:

a plurality of semiconductor memory cells as recited in claim 1 arranged in a matrix of rows and columns.

14. The semiconductor memory array of claim 13, further comprising a plurality of said matrices vertically stacked and electrically connected to form a three-dimensional array.

15. The semiconductor cell of claim 1, further comprising:

a source line terminal electrically connected to one of said first and second regions;

a bit line terminal electrically connected to the other of said first and second regions;

a word line terminal connected to said gate;

a buried well terminal electrically connected to said buried layer, and

a substrate terminal electrically connected to said substrate below said buried layer.

16. The semiconductor memory cell of claim 15, wherein said nonvolatile memory comprises a resistance change element connected to one of said first and second regions, and wherein one of said source line terminal and said bit line terminal is connected to said resistance change element.

17. The semiconductor memory cell of claim 15, wherein a data state of said body region is maintained by applying a voltage to said substrate terminal.

18. The semiconductor memory cell of claim 17, wherein said voltage applied to said substrate terminal automatically activates said cell when said floating body has a first data state to refresh said first data state, and wherein when said body region of said cell has a second data state, said cell automatically remains deactivated upon application of said voltage to said substrate terminal so that said body region of said cell remains in said second data state.

19. The semiconductor memory cell of claim 17, wherein said substrate terminal is periodically biased by pulsing said substrate terminal with said voltage, and wherein said data state of said body region of said cell is refreshed upon each said pulse.

20. The semiconductor memory cell of claim 17, wherein said substrate terminal is constantly biased by application of said voltage thereto, and said body region constantly maintains said data state.

21. The semiconductor memory cell of claim 1, wherein said first and second regions are formed in a fin that extends above said buried layer, said gate is provided on opposite sides of said fin, between said first and second regions, and said body region is between said first and second regions and between said gate on opposite sides of said fin.

22. The semiconductor memory cell of claim 21, wherein said gate is additionally provided above a top surface of said body region.

23. A semiconductor memory cell comprising:

an arrangement of layers having alternating conductivity types selected from p-type conductivity type and n-type conductivity type configured to function as a silicon controlled rectifier device to store data in volatile memory; and

a nonvolatile memory configured to store data upon transfer from volatile memory.

24. The semiconductor memory cell of claim 23, wherein said silicon controlled rectifier device is provided as a P1-N2-P3-N4 silicon-rectifier device.

25. The semiconductor memory cell of claim 24, wherein said cell comprises:

a substrate having a top surface, said substrate having a p-type conductivity type;

a first region having an n-type conductivity type said first region being formed in said substrate and exposed at said top surface;

a second region having said n-type conductivity type, said second region being formed in said substrate, spaced apart from said first region and exposed at said top surface;

a buried layer in said substrate below said first and second regions, spaced apart from said first and second regions and having said n-type conductivity type; and

a body region formed between said first and second regions and said buried layer, said body region having said p-type conductivity type;

wherein said substrate functions as the P1 region of said P1-N2-P3-N4 silicon-rectifier device, said buried layer functions as the N2 region of said P1-N2-P3-N4 silicon-rectifier device, said body region functions as the P3 region of said P1-N2-P3-N4 silicon-rectifier device and said first region or said second region functions as the N4 region of said of P1-N2-P3-N4 silicon-rectifier device.

26. The semiconductor memory cell of claim 25, further comprising a gate positioned between said first and second regions and above said top surface.

27. The semiconductor memory cell of claim 26, wherein said nonvolatile memory comprises a floating gate or trapping layer positioned in between said first and second regions, above said top surface and below said gate.

28. The semiconductor memory cell of claim 26, wherein said nonvolatile memory comprises a resistance change element connected to one of said first and second regions.

29. A method of operating a memory cell having a floating body for storing, reading and writing data as volatile memory, and a nonvolatile memory for storing data, the method comprising:

reading and storing data to the floating body while power is applied to the memory cell;

biasing a substrate terminal connected to a substrate of said memory cell to operate said memory cell as a silicon rectifier device in a conducting operation when said floating body has a first data state, but wherein a blocking operation results when said floating body has a second data state; and

transferring the data stored in the floating body to the nonvolatile memory when power to the cell is interrupted.

30. A method of operating a semiconductor storage device comprising a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory, and a resistance change element for storing data as non-volatile memory, the method comprising:

reading and storing data to the floating bodies as volatile memory while power is applied to the device;

biasing a substrate terminal connected to a substrate of said memory cell to operate said memory cell as a silicon rectifier device in a conducting operation when said floating body has a first data state, but wherein a blocking operation results when said floating body has a second data state;

transferring the data stored in the floating bodies, by a parallel, non-algorithmic process, to the resistance change elements corresponding to the floating bodies, when power to the device is interrupted; and

storing the data in the resistance change elements as non-volatile memory.

31. The method of claim 30, further comprising:

transferring the data stored in the resistance change elements, by a parallel, non-algorithmic, restore process, to the floating bodies corresponding to the resistance change elements, when power is restored to the cell;

and storing the data in the floating bodies as volatile memory.

32. A semiconductor memory cell formed in a vertical arrangement to provide a compact cell size, said cell comprising:

a thin capacitively coupled thyristor access device; and

a resistance change memory.

33. The semiconductor memory cell of claim 32, wherein said thin capacitively coupled thyristor access device functions as select device and said resistance change memory functions as nonvolatile memory.

34. The semiconductor memory cell of claim 32, wherein said thin capacitively coupled thyristor access device comprises a stack of four layers forming p-n-p-n regions.

35. The semiconductor memory cell of claim 32, wherein said resistance change memory comprises a bottom electrode, a chalcogenide material and a top electrode.

36. A semiconductor memory array, including:

a plurality of semiconductor memory cells as recited in claim 32 arranged in a matrix of rows and columns.

37. The semiconductor memory array of claim 36, further comprising a plurality of said matrices vertically stacked and electrically connected to form a three-dimensional array.

38. A method of making a semiconductor memory array, said method comprising:

depositing a conductor layer on an insulator layer;

depositing a polysilicon layer on said conductor layer;

doping said polysilicon layer to form an n-type region;

patterning and etching said conductor layer and polysilicon layer to form column lines of the array;

depositing an insulator layer on the polysilicon layer;

forming holes through the insulator layer;

depositing polysilicon films to fill the holes;

ion implanting the polysilicon films to form p-n-p regions;

patterning and etching the insulator layer to form row lines of the array;

depositing a thin insulating layer;

depositing polysilicon to form a gate;

depositing an additional insulating layer;

depositing a bottom electrode, a resistance change material and a top electrode;

patterning and etching the layers to form rows; and

depositing an insulating layer to cap the resulting layers.