Semiconductor memory device operational processing device and storage system
First Claim
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1. A semiconductor integrated circuit comprising:
- a memory unit including (i) a plurality of memory regions each having a plurality of memory cells each nonvolatilely storing information, each memory region storing different attribute from others, (ii) a plurality of buses arranged corresponding to said plurality of memory regions and separately from each other, and (iii) a plurality of port connection control circuits arranged corresponding to said plurality of memory regions, each for selectively coupling a corresponding memory region to said plurality of buses, each port connection control circuit including a sub-circuit for selectively inhibiting writing of information in a corresponding memory region in accordance with an attribute of the information stored in a corresponding memory region; and
a processor for transferring the information with said plurality of buses.
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Abstract
A thin film magnetic memory includes a size-variable Read Only Memory (ROM) region and a size-variable Random Access Memory (RAM) coupled to different ports for parallel access to the ports, respectively. A memory system allowing fast and efficient data transfer can be achieved.
30 Citations
2 Claims
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1. A semiconductor integrated circuit comprising:
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a memory unit including (i) a plurality of memory regions each having a plurality of memory cells each nonvolatilely storing information, each memory region storing different attribute from others, (ii) a plurality of buses arranged corresponding to said plurality of memory regions and separately from each other, and (iii) a plurality of port connection control circuits arranged corresponding to said plurality of memory regions, each for selectively coupling a corresponding memory region to said plurality of buses, each port connection control circuit including a sub-circuit for selectively inhibiting writing of information in a corresponding memory region in accordance with an attribute of the information stored in a corresponding memory region; and a processor for transferring the information with said plurality of buses.
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2-3. -3. (canceled)
Specification
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Current AssigneeRenesas Electronics Corporation
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Original AssigneeRenesas Technology Corporation (Renesas Electronics Corporation)
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InventorsHidaka, Hideto
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current365/189.11
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CPC Class CodesG11C 11/005 comprising combined but ind...
