SEMICONDUCTOR MEMORY APPARATUS HAVING A SUB-WORD LINE DRIVER FOR INCREASING AN AREA MARGIN IN THE MEMORY CORE AREA

• US 20090316513A1
• Filed: 12/29/2008
• Published: 12/24/2009
• Est. Priority Date: 06/24/2008
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Na, Eun Sung
• Granted Patent: US 7,898,898 B2
• Time in Patent Office: Days
• US Class Current: 365/230.60
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

A semiconductor memory apparatus with a sub-word line driver is presented which has an increased area margin in the memory core area. The sub-word line driver is configured to operate in response to activation of a main word line and in response to positive and negative sub-word line enable signals. The sub-word line driver includes a pull-up driver and a pull-down driver. The pull-up driver is configured to pull-up drive a first sub-word line to the potential level of the positive sub-word line enable signal in response to the activation of the main word line. The pull-down driver is configured to pull-down drive the first sub-word line in response to the negative sub-word line enable signal.

Claims

1. A semiconductor memory apparatus comprising:

a sub-word line driver configured to operate in response to an activation of a main word line and in response to positive and negative sub-word line enable signals,

wherein the sub-word line driver includes;

a pull-up driver configured to pull-up drive a first sub-word line to a potential level of the positive sub-word line enable signal in response to the activation of the main word line; and

a pull-down driver configured to pull-down drive the first sub-word line in response to the negative sub-word line enable signal.

2. The semiconductor memory apparatus of claim 1, wherein the positive and negative sub-word line enable signals are generated from a row decoder,

wherein the positive sub-word line enable signal is at a level of a boosted voltage, when the positive sub-word line enable signal is enabled,

wherein the positive sub-word line enable signal is at a level of a ground voltage, when the positive sub-word line enable signal is disabled,

and wherein the negative sub-word line enable signal has a level opposite in magnitude to the level of the boosted voltage of the positive sub-word line enable signal.

3. The semiconductor memory apparatus of claim 1, wherein the pull-up driver includes a PMOS transistor configured to have a gate terminal connected to the main word line, a source terminal configured to receive the positive sub-word line enable signal, and a drain terminal connected to the first sub-word line.

4. The semiconductor memory apparatus of claim 1, wherein the pull-down driver includes an NMOS transistor configured to have a gate terminal configured to receive the negative sub-word line enable signal, a drain terminal connected to the first sub-word line, and a source terminal that is grounded.

5. The semiconductor memory apparatus of claim 1, further comprising a sub-word line share unit configured to allow the first sub-word line and a second sub-word line adjacent to the first sub-word line to share a potential in response to the activation of the main word line.

6. The semiconductor memory apparatus of claim 5, wherein the sub-word line share unit disconnects the first sub-word line from the second sub-word line when the main word line is activated, and wherein the sub-word line share unit connects the first sub-word line to the second sub-word line when the main word line is deactivated so that the first sub-word line and the second sub-word line share a potential level.

7. A semiconductor memory apparatus comprising:

a first sub-word line driver configured to activate a first sub-word line in accordance to first positive and negative sub-word line enable signals in response to activation of a main word line;

a second sub-word line driver configured to activate a second sub-word line in accordance to control of second positive and negative sub-word line enable signals in response to the activation of the main word line; and

a sub-word line share unit configured to allow the first sub-word line and the second sub-word line to commonly share a potential in response to the activation of the main word line.

8. The semiconductor memory apparatus of claim 7, wherein the first and second positive and negative sub-word line enable signals are generated from a row decoder,

wherein the first and second positive sub-word line enable signals have a level of a boosted voltage when the first and second positive sub-word line enable signals are enabled,

wherein the first and second positive sub-word line enable signals have a level of ground voltage when the first and second positive sub-word line enable signal are disabled

and wherein the first and second negative sub-word line enable signals have levels opposite in magnitude to levels of the first and second positive sub-word line enable signals.

9. The semiconductor apparatus of claim 7, wherein the first sub-word line driver includes:

a pull-up driver configured to pull-up drive the first sub-word line in response to activation of the main word line and in response to the first positive sub-word line enable signal; and

a pull-down driver configured to pull-down drive the first sub-word line in response to the first negative sub-word line enable signal.

10. The semiconductor apparatus of claim 7, wherein the second sub-word line driver includes:

a pull-up driver configured to pull-up drive the second sub-word line in response to activation of the main word line and in response to the second positive sub-word line enable signal; and

a pull-down driver configured to pull-down drive the second sub-word line in response to the second negative sub-word line enable signal.

11. The semiconductor memory of claim 7, wherein the sub-word line share unit disconnects the first sub-word line from the second sub-word line when the main word line is activated, and the sub-word line share unit connects the first sub-word line to the second sub-word line when the main word line is deactivated so that the first sub-word line and the second sub-word line share a potential level.