DECISION FEEDBACK EQUALIZER (DFE)

• US 20090316769A1
• Filed: 06/22/2009
• Published: 12/24/2009
• Est. Priority Date: 06/20/2008
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Hidaka, Yasuo, Gai, Weixin
• Granted Patent: US 8,270,464 B2
• Time in Patent Office: Days
• US Class Current: 375/233
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence

Abstract

In one embodiment, a method includes receiving an input signal from a receiver, receiving a data clock (DCLK) signal, and receiving a boundary clock (BCLK) signal. The method includes, based on the input signal and the DCLK signal, recovering data from the input signal to produce a first output signal. The method includes, based on the input signal and the BCLK signal, recovering boundaries between bits in the input signal to produce a second output signal. The method includes, based on the first and second output signals, producing the DCLK and BCLK signals, with the DCLK signal being delayed with respect to the BCLK signal less than approximately 0.5 unit intervals (UIs) and greater than or equal to approximately zero UIs.

Claims

1. A system comprising:

a data decision latch (DL) comprising a decision feedback equalizer (DFE) and a data slicer and being operable to;

receive an input signal from a receiver, the input signal comprising intersymbol interference (ISI) when communicated from the receiver;

receive a data clock (DCLK) signal; and

based on the input signal and the DCLK signal, recover data from the input signal to produce a first output signal;

a boundary DL comprising a boundary slicer and excluding a DFE and being operable to;

receive the input signal from the receiver;

receive a boundary clock (BCLK) signal; and

based on the input signal and the BCLK signal, recover boundaries between bits in the input signal to produce a second output signal; and

a clock and data recovery (CDR) circuit operable to;

receive the first and second output signals; and

based on the first and second output signals, produce the DCLK and BCLK signals, with the DCLK signal being delayed with respect to the BCLK signal less than approximately 0.5 unit intervals (UIs) and greater than or equal to approximately zero UIs.

2. The system of claim 1, wherein, to produce the DCLK signal, the CDR circuit is operable to produce first the BCLK signal based on the first and second output signals and then delay the BCLK signal by between less than approximately 0.5 UIs and greater than or equal to approximately zero UIs.

3. The system of claim 1, wherein, to produce the BCLK signal, the CDR circuit is operable to produce first the DCLK signal based on the first and second output signals and then delay the DCLK signal by between greater than approximately 0.5 UIs and less than or equal to approximately one UI.

4. The system of claim 1, wherein:

to produce the BCLK signal, the CDR circuit is operable to delay a common reference clock signal by a first delay; and

to produce the DCLK signal, the CDR circuit is operable to delay the common reference clock signal by a second delay;

a difference between the first and second delays causing the DCLK signal to be delayed with respect to the BCLK signal less than approximately 0.5 UIs and greater than or equal to approximately zero UIs.

5. The system of claim 1, wherein:

to produce the BCLK signal, the CDR circuit is operable to merge first and second 90°

phase-shifted reference clock signals with each other at a first weight ratio; and

to produce the DCLK signal, the CDR circuit is operable to merge the first and second 90°

phase-shifted reference clock signals at a second weight ratio;

a difference between the first and second weight ratios causing the DCLK signal to be delayed with respect to the BCLK signal less than approximately 0.5 UIs and greater than or equal to approximately zero UIs.

6. The system of claim 1, wherein the data and boundary DLs are operable to receive the input signal from the receiver via a continuous-time linear equalizer (CTLE) that is operable to substantially cancel the ISI in the input signal.

7. The system of claim 1, wherein the delay from the DCLK signal to the BCLK signal is approximately 0.3 UIs.

8. The system of claim 1, wherein the DFE in the data DL is a speculative 1-tap DFE.

9. The system of claim 1, wherein the data DL is an interleaved data DL, the boundary DL is an interleaved boundary DL, and the DCLK and BCLK signals are sub-rate clock signals.

10. The system of claim 1, wherein the CDR circuit is operable to produce the DCLK and BCLK signals based on a reference clock signal in addition to the first and second output signals.

11. A method comprising:

by a data decision latch (DL) comprising a decision feedback equalizer (DFE) and a data slicer;

receiving an input signal from a receiver, the input signal comprising intersymbol interference (ISI) when communicated from the receiver;

receiving a data clock (DCLK) signal; and

based on the input signal and the DCLK signal, recovering data from the input signal to produce a first output signal;

by a boundary DL comprising a boundary slicer and excluding a DFE;

receiving the input signal from the receiver;

receiving a boundary clock (BCLK) signal; and

based on the input signal and the BCLK signal, recovering boundaries between bits in the input signal to produce a second output signal; and

by a clock and data recovery (CDR) circuit;

receiving the first and second output signals; and

based on the first and second output signals, producing the DCLK and BCLK signals, with the DCLK signal being delayed with respect to the BCLK signal less than approximately 0.5 unit intervals (UIs) and greater than or equal to approximately zero UIs.

12. The method of claim 11, wherein producing the DCLK signal comprises producing first the BCLK signal based on the first and second output signals and then delaying the BCLK signal by between less than approximately 0.5 UIs and greater than or equal to approximately zero UIs.

13. The method of claim 11, wherein producing the BCLK signal comprises producing first the DCLK signal based on the first and second output signals and then delaying the DCLK signal by between greater than approximately 0.5 UIs and less than or equal to approximately one UI.

14. The method of claim 11, wherein:

producing the BCLK signal comprises delaying a common reference clock signal by a first delay; and

producing the DCLK signal comprises delaying the common reference clock signal by a second delay;

a difference between the first and second delays causing the DCLK signal to be delayed with respect to the BCLK signal less than approximately 0.5 UIs and greater than or equal to approximately zero UIs.

15. The method of claim 11, wherein:

producing the BCLK signal comprises merging first and second 90°

phase-shifted reference clock signals with each other at a first weight ratio; and

producing the DCLK signal comprises merging the first and second 90°

phase-shifted reference clock signals at a second weight ratio;

a difference between the first and second weight ratios causing the DCLK signal to be delayed with respect to the BCLK signal less than approximately 0.5 UIs and greater than or equal to approximately zero UIs.

16. The method of claim 11, further comprising receiving by the data and boundary DLs the input signal from the receiver via a continuous-time linear equalizer (CTLE) that is operable to substantially cancel the ISI in the input signal.

17. The method of claim 11, wherein the delay from the DCLK signal to the BCLK signal is approximately 0.3 UIs.

18. The method of claim 11, wherein the DFE in the data DL is a speculative 1-tap DFE.

19. The method of claim 11, wherein the data DL is an interleaved data DL, the boundary DL is an interleaved boundary DL, and the DCLK and BCLK signals are sub-rate clock signals.

20. The method of claim 11, wherein the CDR circuit is operable to produce the DCLK and BCLK signals based on a reference clock signal in addition to the first and second output signals.

21. A system comprising:

means for receiving an input signal from a receiver, the input signal comprising intersymbol interference (ISI) when communicated from the receiver;

means for receiving a data clock (DCLK) signal;

means for receiving a boundary clock (BCLK) signal;

means for, based on the input signal and the DCLK signal, recovering data from the input signal to produce a first output signal;

means for, based on the input signal and the BCLK signal, recovering boundaries between bits in the input signal to produce a second output signal; and

means for, based on the first and second output signals, producing the DCLK and BCLK signals, with the DCLK signal being delayed with respect to the BCLK signal less than approximately 0.5 unit intervals (UIs) and greater than or equal to approximately zero UIs.