ADAPTIVE CONTROL OF A DECISION FEEDBACK EQUALIZER (DFE)

• US 20090316770A1
• Filed: 06/22/2009
• Published: 12/24/2009
• Est. Priority Date: 06/20/2008
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Hidaka, Yasuo
• Application Number:
  US12/489,348
• Publication Number:
  US 20090316770A1
• Time in Patent Office: Days
• US Class Current: 375/233
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 2025/03681 Control of adaptation
• CPC Class Codes: H04L 2025/03783 Details of reference signals
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 7/0025 interpolation of clock signal

Abstract

In one embodiment, a system includes one or more DFEs, each of which includes a feedback (FB) loop to compensate for distortion in an output signal that includes information recovered by a decision circuit from an input signal from a receiver. A first FB tap of a data DFE delays a first output signal of a first decision circuit by approximately 1.0 UIs and multiplies the 1.0-UI-delayed first output signal by a first data FB coefficient derived from a first boundary FB coefficient. A first FB tap of a boundary DFE delays the first output signal by approximately 1.5 UIs and multiplies the 1.5-UI-delayed first output signal by the first boundary FB coefficient, which corresponds to ISI at approximately 1.5 UIs of delay in the input signal.

Claims

1. A system comprising:

a data decision feedback equalizer (DFE) comprising a first decision circuit and one or more data feedback (FB) taps, a first one of the data FB taps being configured to;

delay a first output signal of the first decision circuit by approximately 1.0 unit intervals (UIs), the first output signal comprising data values recovered by the first decision circuit from an input signal from a receiver; and

multiply the 1.0-UI-delayed first output signal by a first data FB coefficient derived from a first boundary FB coefficient; and

a boundary DFE comprising a second decision circuit and one or more boundary FB taps,

a first one of the boundary FB taps being configured to;

delay the first output signal by approximately 1.5 UIs; and

multiply the 1.5-UI-delayed first output signal by the first boundary FB coefficient, the first boundary FB coefficient corresponding to residual intersymbol interference (ISI) at approximately 1.5 UIs of delay in the input signal.

2. The system of claim 1, wherein:

a second one of the data FB taps is configured to;

delay the first output signal by approximately 2.0 UIs; and

multiply the 2.0-UI-delayed first output signal by a second data FB coefficient derived from the first boundary FB coefficient and a second boundary FB coefficient; and

a second one of the boundary FB taps is configured to;

delay the first output signal by approximately 2.5 UIs; and

multiply the 2.5-UI-delayed first output signal by the second boundary FB coefficient, the second boundary FB coefficient corresponding to residual ISI at approximately 2.5 UIs of delay in the input signal.

3. The system of claim 1, wherein:

an n^th one of the data FB taps is configured to;

delay the first output signal by approximately n UIs; and

multiply the n-UI-delayed first output signal by an n^th data FB coefficient derived from an (n−

1)^th boundary FB coefficient and an n^th boundary FB coefficient; and

an n^th one of the boundary FB taps is configured to;

delay the first output signal by approximately n+0.5 UIs; and

multiply the (n+0.5)-UI-delayed first output signal by the n^th boundary FB coefficient, the n^th boundary FB coefficient corresponding to residual ISI at approximately n+0.5 UIs of delay in the input signal.

4. The system of claim 1, wherein the first data FB coefficient is derived from the first boundary FB coefficient at least in part by scaling the first boundary FB coefficient by a predetermined value.

5. The system of claim 1, further comprising a controller configured to receive the first output signal of the first decision circuit and a second output signal of the second decision circuit and produce the data and boundary FB coefficients based on the first and second output signals, the second output signal comprising boundary values recovered by the second decision circuit from the input signal.

6. The system of claim 1, wherein:

the system further comprises a clock and data recovery (CDR) circuit configured to;

receive the first output signal of the first decision circuit and a second output signal of the second decision circuit, the second output signal comprising boundary values recovered by the second decision circuit from the input signal;

detect phase error in the input signal based on the first and second output signals; and

produce data clock (DCLK) and boundary clock (BCLK) signals based on the phase error;

the first decision circuit is configured to recover data values from the input signal based on the DCLK signal and a first feedback signal from the one or more data FB taps; and

the second decision circuit is configured to recover boundary values from the input signal based on the BCLK signal and a second feedback signal from the one or more boundary FB taps.

7. A method comprising:

by a first one of one or more data feedback (FB) taps in a data decision feedback equalizer (DFE) comprising a first decision circuit and the one or more data feedback (FB) taps;

delaying a first output signal of the first decision circuit by approximately 1.0 unit intervals (UIs), the first output signal comprising data values recovered by the first decision circuit from an input signal from a receiver; and

multiplying the 1.0-UI-delayed first output signal by a first data FB coefficient derived from a first boundary FB coefficient; and

by first one of one or more boundary FB taps in a boundary DFE comprising a second decision circuit and the one or more boundary FB taps;

delaying the first output signal by approximately 1.5 UIs; and

multiplying the 1.5-UI-delayed first output signal by the first boundary FB coefficient, the first boundary FB coefficient corresponding to residual intersymbol interference (ISI) at approximately 1.5 UIs of delay in the input signal.

8. The method of claim 7, further comprising:

by a second one of the data FB taps;

delaying the first output signal by approximately 2.0 UIs; and

multiplying the 2.0-UI-delayed first output signal by a second data FB coefficient derived from the first boundary FB coefficient and a second boundary FB coefficient; and

by a second one of the boundary FB taps;

delaying the first output signal by approximately 2.5 UIs; and

multiplying the 2.5-UI-delayed first output signal by the second boundary FB coefficient, the second boundary FB coefficient corresponding to residual ISI at approximately 2.5 UIs of delay in the input signal.

9. The method of claim 7, further comprising:

by an n^th one of the data FB taps;

delaying the first output signal by approximately n UIs; and

multiplying the n-UI-delayed first output signal by an n^th data FB coefficient derived from an (n−

1)^th boundary FB coefficient and an n^th boundary FB coefficient; and

by an n^th one of the boundary FB taps;

delaying the first output signal by approximately n+0.5 UIs; and

multiplying the (n+0.5)-UI-delayed first output signal by the n^th boundary FB coefficient, the n^th boundary FB coefficient corresponding to residual ISI at approximately n+0.5 UIs of delay in the input signal.

10. The method of claim 7, wherein the first data FB coefficient is derived from the first boundary FB coefficient at least in part by scaling the first boundary FB coefficient by a predetermined value.

11. The method of claim 7, further comprising, by a controller:

receiving the first output signal of the first decision circuit and a second output signal of the second decision circuit; and

producing the data and boundary FB coefficients based on the first and second output signals, the second output signal comprising boundary values recovered by the second decision circuit from the input signal.

12. The method of claim 7, further comprising:

by a clock and data recovery (CDR) circuit;

receiving the first output signal of the first decision circuit and a second output signal of the second decision circuit, the second output signal comprising boundary values recovered by the second decision circuit from the input signal;

detecting phase error in the input signal based on the first and second output signals; and

producing data clock (DCLK) and boundary clock (BCLK) signals based on the phase error;

by the first decision circuit, recovering data values from the input signal based on the DCLK signal and a first feedback signal from the one or more data FB taps; and

by the second decision circuit, recovering boundary values from the input signal based on the BCLK signal and a second feedback signal from the one or more boundary FB taps.

13. A system comprising:

means for;

delaying by approximately 1.0 unit intervals (UIs) a first output signal of a first decision circuit in a first one of one or more data feedback (FB) taps in a data decision feedback equalizer (DFE), the first output signal comprising data values recovered by the first decision circuit from an input signal from a receiver; and

multiplying the 1.0-UI-delayed first output signal by a first data FB coefficient derived from a first boundary FB coefficient; and

means for;

delaying the first output signal by approximately 1.5 UIs; and

multiplying the 1.5-UI-delayed first output signal by the first boundary FB coefficient, the first boundary FB coefficient corresponding to residual intersymbol interference (ISI) at approximately 1.5 UIs of delay in the input signal.

14. The system of claim 13, further comprising:

means for;

delaying the first output signal by approximately 2.0 UIs; and

multiplying the 2.0-UI-delayed first output signal by a second data FB coefficient derived from the first boundary FB coefficient and a second boundary FB coefficient; and

means for;

delaying the first output signal by approximately 2.5 UIs; and

multiplying the 2.5-UI-delayed first output signal by the second boundary FB coefficient, the second boundary FB coefficient corresponding to residual ISI at approximately 2.5 UIs of delay in the input signal.

15. The system of claim 13, further comprising:

means for;

delaying the first output signal by approximately n UIs; and

multiplying the n-UI-delayed first output signal by an n^th data FB coefficient derived from an (n−

1)^th boundary FB coefficient and an n^th boundary FB coefficient; and

means for;

delaying the first output signal by approximately n+0.5 UIs; and

multiplying the (n+0.5)-UI-delayed first output signal by the n^th boundary FB coefficient, the n^th boundary FB coefficient corresponding to residual ISI at approximately n+0.5 UIs of delay in the input signal.

16. The system of claim 13, wherein the first data FB coefficient is derived from the first boundary FB coefficient at least in part by scaling the first boundary FB coefficient by a predetermined value.

17. The system of claim 13, further comprising means for:

receiving the first output signal of the first decision circuit and a second output signal of the second decision circuit; and

producing the data and boundary FB coefficients based on the first and second output signals, the second output signal comprising boundary values recovered by the second decision circuit from the input signal.

18. The system of claim 13, further comprising:

means for;

receiving the first output signal of the first decision circuit and a second output signal of the second decision circuit, the second output signal comprising boundary values recovered by the second decision circuit from the input signal;

detecting phase error in the input signal based on the first and second output signals; and

producing data clock (DCLK) and boundary clock (BCLK) signals based on the phase error;

means for recovering data values from the input signal based on the DCLK signal and a first feedback signal from the one or more data FB taps; and

means for recovering boundary values from the input signal based on the BCLK signal and a second feedback signal from one or more boundary FB taps in a boundary DFE.