HARDWARE ACCELERATION FOR WWAN TECHNOLOGIES

• US 20090316904A1
• Filed: 06/18/2009
• Published: 12/24/2009
• Est. Priority Date: 06/19/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Narayan, Sriram, Khan, Irfan A., Tran, Jean-Marie QD, Chhabra, Gurvinder S., Mir, Idreas, Klingenbrunn, Thomas, Kohlenz, Mathias, Maheshwari, Shailesh, Kumar, Vanitha A., Babbar, Uppinder S., Lioy, Marcello V., Jim, Samson, Nagpal, Vikas
• Granted Patent: US 8,898,448 B2
• Time in Patent Office: Days
• US Class Current: 380/274
• CPC Class Codes: H04L 2209/122 Hardware reduction or efficient architectures
• CPC Class Codes: H04L 2209/26 Testing cryptographic entity, e.g. testing integrity of encryption key or encryption algorithm
• CPC Class Codes: H04L 2209/80 Wireless
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 63/0457 wherein the sending and receiving network entities apply dynamic encryption, e.g. stream encryption cryptographic mechanisms or cryptographic arrangements for stream encryption H04L9/065
• CPC Class Codes: H04L 9/065 Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
• CPC Class Codes: H04W 12/02 Protecting privacy or anonymity, e.g. protecting personally identifiable information [PII]
• CPC Class Codes: H04W 12/037 of the control plane, e.g. signalling traffic
• CPC Class Codes: H04W 80/02 Data link layer protocols
• CPC Class Codes: Y04S 40/20 Information technology specific aspects, e.g. CAD, simulation, modelling, system security

Abstract

Systems and methods for wireless communications are provided. These include data deciphering components, interrupt processing components, adaptive aggregations methods, optimized data path processing, buffer pool processing, application processing where data is formatted in a suitable format for a destination process, and Keystream bank processing among other hardware acceleration features. Such systems and methods are provided to simplify logic designs and mitigate processing steps during wireless network data processing.

Claims

1. A method of deciphering packetized data in a telecommunications signal with a hyper framer number (HFN), comprising:

determining the HFN;

testing for a mismatched HFN, wherein if a mismatched HFN is detected,

reconstructing data that was deciphered with the mismatched HFN;

deciphering the data using a correct HFN; and

copying the deciphered data to an external memory after the correct HFN is utilized, where a reduction in copying data to the external memory is achieved when a mismatched HFN is detected.

2. The method of claim 1, further comprising deriving one or more deciphering parameters before copying the deciphered data.

3. The method of claim 2, further comprising deriving a packet sequence number in addition to the HFN.

4. A processor capable of deciphering packetized data in a telecommunications signal with a hyper framer number (HFN), capable of executing instructions for:

determining the HFN;

testing for a mismatched HFN, wherein if a mismatched HFN is found,

reconstructing data that was deciphered with the mismatched HFN;

deciphering the data using a correct HFN; and

copying the deciphered data to an external memory after the correct HFN is utilized, where a reduction in copying data to the external memory is achieved when a mismatched HFN is detected.

5. The processor of claim 4, further comprising deriving a packet sequence number in addition to the HFN.

6. A computer program product, comprising:

a computer readable medium that includes code for deciphering packetized data in a telecommunications signal with a hyper framer number (HFN), the code comprising;

code for causing a computer to determine the HFN;

code for causing a computer to test for a mismatched HFN, wherein if a mismatched HFN is found,

code for causing a computer to reconstruct data that was deciphered with the mismatched HFN; and

code for causing a computer to decipher the data using a correct HFN; and

copying the deciphered data to an external memory after the correct HFN is utilized, where a reduction in copying data to the external memory is achieved when a mismatched HFN is detected.

7. The computer program product of claim 6, the computer readable medium further comprising code for causing a computer to derive a packet sequence number in addition to the HFN.

8. A method of increasing the performance of a telecommunications device by managing interrupts to its modem processor while processing packetized data, comprising:

receiving packetized data;

storing at least one of a time and data volume-based threshold with respect to the received packetized data;

initiating a software interrupt to the modem processor when the packetized data ready to be processed by software exceeds at least one of the time and data volume-based thresholds; and

accumulating the packetized data if no interrupt is initiated, and adjusting at least the time and data volume-based thresholds, in order to reduce frequency of interrupts.

9. The method of claim 8, further comprising adjusting thresholds based on quality of service, on priority, on processing bandwidth, on bus activity, or available battery life.

10. A processor capable of increasing the performance of a telecommunications device by managing interrupts to its modem processor while processing packetized data, capable of executing instructions for:

receiving packetized data;

storing at least one of a time and data thresholds with respect to the received packetized data;

initiating a software interrupt to the modem processor when the packetized data ready to be processed by software exceeds at least one of the time and data thresholds; and

accumulating the packetized data if no interrupt is initiated, where adjusting at least the time and data thresholds, frequency of interrupts are reduced.

11. The processor of claim 10, further comprising adjusting thresholds based on quality of service, on priority, on processing bandwidth, on bus activity, or available battery life.

12. A computer program product, comprising:

a computer readable medium the includes code for increasing the performance of a telecommunications device by managing interrupts to its modem processor while processing packetized data, the code comprising;

code for causing a computer to receive packetized data;

code for causing a computer to store at least one of a time and data volume-based threshold with respect to the received packetized data;

code for causing a computer to initiate a software interrupt to the modem processor when the packetized data ready to be processed by software exceeds at least one of the time and data volume-based thresholds; and

code for causing a computer to accumulate the packetized data if no interrupt is initiated, where adjusting at least the time and data volume-based thresholds, frequency of interrupts are reduced.

13. The computer program product of claim 12, the computer readable medium further comprising code for causing a computer to adjust thresholds based on quality of service, on priority, on processing bandwidth, on bus activity, or available battery life.

14. A method of obtaining efficiencies in processing of functions in a telecommunications device by grouping functions germane to telecommunications processing of packetized data, comprising:

grouping functions relating to at least one of ciphering, deciphering, high-level data link control (HDLC) framing, checksum calculations, and protocol header insertion; and

performing the functions as a group, where bus activity is reduced as compared to performing the functions on a non-group basis.

15. The method of claim 14, where the grouping enables a reduced move of data across hardware in the telecommunications device.

16. The method of claim 14, where two moves of data are employed for performing the group.

17. The method of claim 14, where a function of at least one of ciphering and deciphering is performed after a first move of data.

18. The method of claim 17, wherein partial deciphering for Internet Protocol/Transport Control (IP/TCP) headers are performed after the first move of data.

19. A processor capable of obtaining efficiencies in processing of functions in a telecommunications device by grouping functions germane to telecommunications processing of packetized data, capable of executing instructions for:

grouping functions relating to at least one of ciphering, deciphering, framing, checksum calculations, and protocol header insertion; and

performing the functions as a group, where bus activity is reduced as compared to performing the functions on a non-group basis.

20. The processor of claim 19, where a function of at least one of ciphering and deciphering is performed after a first move of data.

21. A computer program product, comprising:

a computer readable medium that includes code for obtaining efficiencies in processing of functions in a telecommunications device by grouping functions germane to telecommunications processing of packetized data, the code comprising;

code for causing a computer to group functions relating to at least one of ciphering, deciphering, framing, checksum calculations, and protocol header insertion; and

performing the functions in group, where bus activity is reduced as compared to performing the functions on a non-group basis.

22. The computer program product of claim 21, wherein the partial deciphering for Internet Protocol/Transport Control (IP/TCP) headers are performed after the first move of data.

23. A method of providing buffers for a hardware accelerator in a telecommunications device for packetized data, comprising:

providing a dynamic pool of buffers for use by the hardware accelerator, where access to the pool of buffers is controlled by software in the telecommunications device, where the software dynamically adjusts the pool of buffers according to hardware needs indicated by at least one of status signals from the hardware and threshold information on the pool of buffers, where buffers in the pool are replenished via software control.

24. The method of claim 23, the status signals are associated with an interrupt that is timed during reduced processor activities.

25. A processor capable providing buffers for a hardware accelerator in telecommunications device for packetized data, capable of executing instructions for:

providing a dynamic pool of buffers for use by the hardware accelerator, where access to the pool of buffers is controlled by software in the telecommunications device, where the software dynamically adjusts the pool of buffers according to hardware needs indicated by at least one of status signals from the hardware and threshold information on the pool of buffers, where buffers in the pool are replenished via software control.

26. The processor of claim 25, the status signals are associated with an interrupt that is timed during reduced processor activities.

27. A computer program product, comprising:

a computer readable medium that includes code for a hardware accelerator in a telecommunications device for packetized data, the code comprising;

code for causing a computer to provide a dynamic pool of buffers for use by the hardware accelerator, where access to the pool of buffers is controlled by software in the telecommunications device, where the software dynamically adjusts the pool of buffers according to hardware needs indicated by at least one of status signals from the hardware and threshold information on the pool of buffers, where buffers in the pool are replenished via software control.

28. The computer program product of claim 27, the status signals are associated with an interrupt that is timed during reduced processor activities.

29. An apparatus capable providing buffers for a hardware accelerator in a telecommunications device for packetized data, comprising:

means for providing a dynamic pool of buffers for use by the hardware accelerator, where access to the pool of buffers is controlled by the means for providing in the telecommunications device; and

means for dynamically adjusting the pool of buffers according to hardware needs indicated by at least one of status signals from the hardware and threshold information on the pool of buffers, where buffers in the pool are replenished via the means for providing.

30. The apparatus of claim 29, further comprising means for analyzing cache-aligned memory locations.

31. A method for reducing duplicate copies of data during read and write operations between target and source modules in a telecommunications device for packetized data, comprising:

signaling a target module by a source module in the telecommunications device that data is to be copied to the target module;

sending a target-specific structure by the target module to the source module;

receiving the target-specific structure by the source module;

populating data into the target-specific structure by the source module; and

receiving the target-specific populated data by the target module, where one copy of data having the target-specific structure is created.

32. The method of claim 31, the target-specific structure is associated with a network driver interface specification (NDIS).

33. A processor capable of reducing duplicate copies of data during read and write operations between target and source modules in a telecommunications device for packetized data, capable of executing instructions for:

signaling a target module by a source module in the telecommunications device that data is to be copied to the target module;

sending a target-specific structure by the target module to the source module;

receiving the target-specific structure by the source module;

populating data into the target-specific structure by the source module; and

receiving the target-specific populated data by the target module, where one copy of data having the target-specific structure is created.

34. The processor of claim 33, the target-specific structure is associated with a network driver interface specification (NDIS).

35. A computer program product, comprising:

a computer readable medium that includes code for reducing duplicate copies of data during read and write operations between target and source modules in a telecommunications device for packetized data, the code comprising;

code for causing a computer to signal a target module by a source module in the telecommunications device that data is to be copied to the target module;

code for causing a computer to send a target-specific structure by the target module to the source module;

code for causing a computer to receive the target-specific structure by the source module;

code for causing a computer to populate data into the target-specific structure by the source module; and

code for causing a computer to receive the target-specific populated data by the target module, where one copy of data having the target-specific structure is created.

36. The computer program product of claim 35, the target-specific structure is associated with a network driver interface specification (NDIS).

37. A method of reducing data moves for a keystream generation in a telecommunications device, comprising:

programming ciphering parameters to hardware;

pre-computing keystreams for a number of packets in advance by the hardware;

storing the pre-computed keystreams in a bank; and

providing a suitable keystream for data flow to software, where the bank of keystreams is tested for keystream sufficiency when a keystream is requested by software, where processing overhead to program additional keystreams is minimized by use of the pre-computed keystreams.

38. The method of claim 37, the ciphered parameters are associated with protocol data units.

39. A processor capable of reducing data moves for a keystream generation in a telecommunications device, capable of executing instructions for:

programming ciphering parameters to hardware;

pre-computing keystreams for a number of packets in advance by the hardware;

storing the pre-computed keystreams in a bank; and

providing a suitable keystream for data flow to software, where the bank of keystreams is tested for keystream sufficiency when a keystream is requested by software, where processing overhead to program additional keystreams is minimized by use of the pre-computed keystreams.

40. The processor of claim 39, the ciphered parameters are associated with protocol data units.

41. A computer program product, comprising:

a computer readable medium that includes code for reducing data moves for a keystream generation in a telecommunications device, the code comprising;

code for causing a computer to program ciphering parameters to hardware;

code for causing a computer to pre-compute keystreams for a number of packets in advance by the hardware;

code for causing a computer to store the pre-computed keystreams in a bank; and

code for causing a computer to provide a suitable keystream for data flow to software, where the bank of keystreams is tested for keystream sufficiency when a keystream is requested by software, where processing overhead to program additional keystreams is minimized by use of the pre-computed keystreams.

42. The computer program product of claim 41, the ciphered parameters are associated with protocol data units.