MOLDED RECONFIGURED WAFER, STACK PACKAGE USING THE SAME, AND METHOD FOR MANUFACTURING THE STACK PACKAGE

• US 20090317944A1
• Filed: 08/24/2009
• Published: 12/24/2009
• Est. Priority Date: 06/18/2007
• Status: Active Grant

• Current Assignee: Jong Hoon Kim
• Original Assignee: Jong Hoon Kim
• Inventors: KIM, Jong Hoon
• Granted Patent: US 7,763,498 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06565 : the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A stack package includes at least two stacked package units. Each package unit comprises semiconductor chips having bonding pads on upper surfaces thereof; a molding part formed to surround side surfaces of the semiconductor chips; through-electrodes formed in the molding part; and re-distribution lines formed to connect the through-electrodes and adjacent bonding pads with each other.

Claims

1. A method for manufacturing a stack package, comprising the steps of:

providing a molded reconfigured wafer having a plurality of semiconductor chips arranged side by side, each of which having a plurality of bonding pads on a upper surface thereof, and a molding part surrounding side and lower surfaces of each semiconductor chip;

defining grooves in the molding part adjacent to the bonding pads of each semiconductor chip;

forming through-electrodes in the grooves and forming re-distribution lines which connect the through-electrodes and the adjacent bonding pads to each other;

removing a portion of the lower surface of the molded reconfigured wafer so as to expose the lower surfaces of the through-electrodes so as to form a plurality of package units in the molded reconfigured wafer;

stacking at least two molded reconfigured wafers, wherein the package units from each of the stacked wafers are stacked such that corresponding through-electrodes are connected with each other; and

sawing the stacked package units of the stacked molded reconfigured wafers into a chip level.

2. The method according to claim 1, wherein each groove is defined to have a depth which is deeper than the lower surface of each semiconductor chip.

3. The method according to claim 1, wherein the step of forming the through-electrodes and the re-distribution lines comprises the steps of:

forming a metal seed layer on an upper surface of the molded reconfigured wafer including the grooves;

forming a metal layer on the metal seed layer to fill the grooves; and

patterning the metal layer and the metal seed layer.

4. The method according to claim 1, wherein, after the step of forming the metal layer and before the step of patterning the metal layer and the metal seed layer, the method further comprises the step of:

etching back the metal layer to reduce a thickness of the metal layer.

5. The method according to claim 1, wherein removal of the lower surfaces of the molded reconfigured wafers is conducted using at least one of a grinding process and an etching process such that molding parts are removed on the lower surfaces of the molded reconfigured wafers.

6. The method according to claim 1, wherein, after the step of stacking the package units, the method further comprises the step of:

filling a filler material between the stacked package units and forming a capping layer on an uppermost package unit.

7. The method according to claim 1, wherein the stacked package units have their respective semiconductor chips which have different sizes.

8. The method according to claim 1, wherein, after the step of sawing the package units into a chip level, the method further comprises the step of:

attaching the stacked package units which are formed with the through-electrodes, to the substrate.

9. The method according to claim 8, further comprising the step of:

filling a filler material between a lowermost package unit attached to the substrate and the substrate.

10. The method according to claim 8, wherein, after the step of attaching the stacked package units to the substrate, the method further comprises the step of:

forming an encapsulant to fill between the stacked package units and between a lowermost package unit and the substrate and to cover an upper surface of the substrate including an upper surface of an uppermost package unit.

11. The method according to claim 8, wherein, after the step of attaching the stacked package units to the substrate, the method further comprises the step of:

attaching outside connection terminals to a lower surface of the substrate.