METHOD FOR PROVIDING AND REMOVING DISCHARGING INTERCONNECT FOR CHIP-ON-GLASS OUTPUT LEADS AND STRUCTURES THEREOF

• US 20090317946A1
• Filed: 08/31/2009
• Published: 12/24/2009
• Est. Priority Date: 02/21/2006
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Chou, Chen-Jean
• Granted Patent: US 7,955,899 B2
• Time in Patent Office: Days
• US Class Current: 438/121
• CPC Class Codes: B81B 2201/047 Optical MEMS not provided for in B81B2201/042 - B81B2201/045
• CPC Class Codes: B81B 7/0022 Protection against electrostatic discharge electrostatic discharge protection for electronic semiconductor circuits H01L27/0248; circuit arrangements for protecting electronic switching circuits used for pulse technique against overcurrent or overvoltage H03K17/08
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2330/04 Display protection

Abstract

Microelectronic devices may be fabricated while being protected from damage by electrostatic discharge. In one embodiment, a shorting circuit is connected to elements of the microelectronic device, where the microelectronic device is part of a chip-on-glass system. In one aspect of this embodiment, a portion of the shorting circuit is in an area of a substrate where a microchip is bonded. In another embodiment, shorting links of the shorting circuit are comprised of a fusible material, where the fusible material may be disabled by an electrical current capable of fusing the shorting links.

Claims

1. A method of providing electrostatic discharge protection during a fabrication process of a micro-electronic device, wherein the microelectronic device comprises an array of electronic devices on a substrate, the method comprising:

applying a plurality of conductive leads to the substrate, wherein the leads connect to the electronic devices;

applying an electrically conductive material to the substrate to serve as a shorting structure;

applying shorting links to the substrate, wherein the shorting links are comprised of an electrically conductive material and are in electrical connection to the conductive leads and the shorting structure; and

wherein the shorting structure is at least partially located in an area of the substrate to attach a microchip and at least one of the group of shorting links or the shorting structure is configured so as to be at least partially removable.

2. The method of claim 1, further comprising applying bond pads in the area of the substrate to attach the microchip.

3. The method of claim 2, further comprising bonding an electronic device to the bond pads.

4. The method of claim 1, further comprising removing at least a portion of the shorting structure or a portion of the group of shorting links, thus disabling the group of shorting links.

5. The method of claim 4, wherein the removing comprises at least one of chemical etching, wet etching, plasma etching, laser etching, and electrical fusing.

6. The method of claim 1, wherein the group of shorting links comprises a fusible material.

7. The method of claim 6, further comprising applying an electrical current across one of the shorting links, the electrical current being sufficient to fuse the shorting link, thus disabling the shorting link.

8. The method of claim 1, wherein the shorting structure comprises an etchable material.

9. The method of claim 8, further comprising:

applying an etch-stop material to at least a portion of the conductive leads and the bond pads; and

etching at least a portion of the shorting structure, thus disabling the group of shorting links.

10. A method of providing electrostatic discharge protection during a fabrication process of a micro-electronic device, wherein the microelectronic device comprises an array of electronic devices on a substrate, the method comprising:

applying a plurality of conductive leads to the substrate, wherein the leads connect to the electronic devices; and

applying shorting links to the substrate in electrical connection with the conductive leads and configuring the shorting links such that all of the conductive leads are connected to a single shorting circuit, wherein the shorting links are comprised of fusible material and are configured so as to be disabled by an electrical current capable of fusing the shorting links.

11. The method of claim 10, further comprising:

applying an electrically conductive material to the substrate to serve as a shorting structure; and

wherein the shorting links are in electrical connection with the conductive leads and the shorting structure.

12. The method of claim 10, further comprising applying an electrical current across one of the shorting links, the electrical current being sufficient to fuse the shorting link, thus disabling the shorting link.

13. The method of claim 10, further comprising applying an electrical current across one of the shorting links, the electrical current being sufficient to fuse the shorting link, thus disabling the shorting link.

14. The method of claim 10, further comprising applying an electrical current across all of the shorting links, the electrical current being sufficient to fuse all of the shorting links, thus disabling the shorting circuit.