STACKED SEMICONDUCTOR MEMORY DEVICE WITH COMPOUND READ BUFFER

• US 20090319703A1
• Filed: 08/05/2008
• Published: 12/24/2009
• Est. Priority Date: 06/23/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chung, Hoe-ju
• Granted Patent: US 7,913,000 B2
• Time in Patent Office: Days
• US Class Current: 710/52
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A stacked memory apparatus operating with a compound read buffer is disclosed. The stacked memory apparatus includes an interface device having a main buffer and a plurality of memory devices each having a device read buffer. Systems incorporating one or more stacked memory apparatuses and related method of performing a read operation are also disclosed.

Claims

1. A stacked memory apparatus providing read data in response to a read command and comprising:

an interface device comprising;

a main control circuit configured to generate a main buffer output signal and a main buffer input signal, and

a main buffer configured to provide the read data to an external circuit in response to the main buffer output signal; and

a plurality of memory devices vertically stacked on the interface device, wherein each memory device in the plurality of memory devices comprises;

a memory core configured to provide the read data in response to a device read signal,

a device buffer configured to receive the read data from the memory core in response to a device buffer input signal and provide the read data to the main buffer in response to a device buffer output signal, and

a device control circuit receiving the read command and the main buffer input signal, and configured to generate the device read signal in response to the read command, the device buffer input signal in relation to a read data access delay associated with the memory core, and the device buffer output signal in relation to the main buffer input signal.

2. The apparatus of claim 1, wherein the interface device is a memory device similar to each one of the plurality of memory devices.

3. The apparatus of claim 1, wherein the interface device is a controller or a master device.

4. The apparatus of claim 1, wherein the main buffer and each device buffer in the plurality of memory devices are respectively First-In First-Out (FIFO) buffers.

5. The apparatus of claim 4, wherein each memory device in the plurality of memory devices further comprises an Input/Output (I/O) driver and each device buffer is configured within a corresponding I/O driver.

6. The apparatus of claim 5, wherein the interface device further comprises a read controller configured to transfer the read data from the main buffer to an external circuit.

7. The apparatus of claim 6, wherein the interface device further comprises a write controller configured to transfer write data from an external circuit to a write buffer, wherein the write buffer is configured to provide the write data from the write controller to an I/O driver in one of the plurality of memory devices.

8. The apparatus of claim 1, wherein the device control circuit comprises:

a first command decoder configured to generate the device read signal in response to the read command; and

a first delay unit configured to generate the device buffer input signal in response to the device read signal.

9. The apparatus of claim 8, wherein the first delay unit comprises a first delay controller receiving the device read signal and delaying the device read signal by the read data access delay to generate the device buffer input signal.

10. The apparatus of claim 8, wherein the main control circuit comprises:

a second command decoder configured to generate a main read signal in response to the read command;

a second delay unit configured to generate the main buffer output signal in response to the main read signal; and

a third delay unit configured to generate the main buffer input signal in response to the main read signal.

11. The apparatus of claim 10, wherein the second delay unit comprises a second delay controller receiving the main read signal and delaying the main read signal by a read data output delay to generate the main buffer output signal, and the third delay unit comprise a third delay controller receiving the main read signal and delaying the main read signal by a read data compensation delay to generate the main buffer input signal.

12. The apparatus of claim 11, wherein the read data output delay is defined in relation to an external clock associated with the read command.

13. The apparatus of claim 1, wherein stack adjacent memory devices in the plurality of memory devices are connected by at least one Through Silicon Via (TSV).

14. The apparatus of claim 13, wherein the plurality of memory devices commonly receive an address signal via a plurality of parallel address signal lines, wherein each one of the plurality of address signal lines comprises a plurality of TSVs, each TSV in the plurality of TSVs respectively extending through one of the plurality of memory devices.

15. The apparatus of claim 14, wherein each memory core in each one of the plurality of memory devices comprises;

a core, a row decoder, a column decoder, and an Input/Output (I/O) driver comprising the device buffer, and

wherein the row decoder and column decoder in at least one responding memory device in the plurality of memory devices selects the read data from the core in accordance with the address signal and provides the selected read data to the device buffer in the I/O driver.

16. The apparatus of claim 14, wherein the plurality of memory devices are selectively controlled by a memory stack control signal communicated to the plurality of memory devices by a serial signal line traversing the stacked plurality of memory devices, wherein the serial signal line comprises a plurality of TSVs each TSV in the plurality of TSVs respectively extending through one of the plurality of memory devices.

17. The apparatus of claim 16, wherein each memory core in each one of the plurality of memory devices comprises;

a core, a row decoder, a column decoder, and an Input/Output (I/O) driver comprising the device buffer, and

wherein the row decoder and column decoder in at least one responding memory device in the plurality of memory devices selects the read data from the core in accordance with the address signal and provides the selected read data to the device buffer in the I/O driver, and the at least one responding memory device is determined by the memory stack control signal.

18. A system comprising:

at least one memory apparatus; and

a processor communicating to the at least one memory apparatus a read command identifying read data,

wherein each one of the at least one memory apparatus comprises an interface device and a plurality of memory devices vertically stacked on the interface device;

the interface device comprising a main control circuit configured to generate a main buffer output signal and a main buffer input signal, and a main buffer configured to provide the read data in response to the main buffer output signal; and

each one of the plurality of memory devices comprising,

a memory core configured to provide the read data in response to a device read signal,

a device buffer configured to receive the read data from the memory core in response to a device buffer input signal and provide the read data to the main buffer in response to a device buffer output signal, and

a device control circuit receiving the read command and the main buffer input signal and configured to generate the device read signal in response to the read command, the device buffer input signal in relation to a read data access delay associated with the memory core, and the device buffer output signal in relation to the main buffer input signal.

19. The system of claim 18, wherein the interface device is one of a memory device, a master memory device, and a memory controller.

20. The system of claim 18, further comprising:

a memory controller receiving the read command from the processor and configured to generate an address signal and a control signal in response to the read command,

wherein the at least one memory apparatus comprises a memory module configured to operatively associate a plurality of memory apparatuses with the memory controller, such that each one of the plurality of memory apparatuses receives the address signal and the control signal.

21. The system of claim 20, further comprising:

a data bridge circuit connecting the processor with the memory controller and configured to communicate the read command from the processor to the memory controller and communicate the read data from at least the one of the plurality of memory apparatuses to a read/write memory associated with the processor.

22. The system of claim 21, further comprising:

a graphics processor connected to the memory controller via the data bridge and configured to receive the read data from at least the one of the plurality of memory apparatuses in response to the read command.

23. The system of claim 18, wherein each one of the at least one memory apparatus is a Dynamic Random Access Memory (DRAM) device or a Static Random Access Memory (SRAM) device.

24. The system of claim 18, wherein each one of the at least one memory apparatus is a non-volatile memory device.

25. The system of claim 24, wherein each one of the at least one memory apparatus is a flash memory device.

26-48. -48. (canceled)