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SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEMS AND ASSOCIATED METHODS

  • US 20090319717A1
  • Filed: 08/28/2009
  • Published: 12/24/2009
  • Est. Priority Date: 05/10/2000
  • Status: Active Grant
First Claim
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1. A multiprocessor system comprising:

  • at least two processors, each processor having at least one processing core;

    at least two memory controllers, each communicatively coupled to one of the at least two processors, to facilitate transactions between a memory and the at least two processors;

    at least one hub for input/output devices;

    at least one bridge to send and receive transactions between the at least one hub for input/output devices and the at least two processors; and

    at least two crossbars, each communicatively coupled to one of the at least two processors, to route the transactions between the at least one hub for input/output devices and the at least two processors;

    wherein the at least two crossbars are each communicatively coupled to one of the at least two memory controllers to route transactions between the at least one hub for input/output devices and the memory.

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