SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEMS AND ASSOCIATED METHODS
First Claim
1. A multiprocessor system comprising:
- at least two processors, each processor having at least one processing core;
at least two memory controllers, each communicatively coupled to one of the at least two processors, to facilitate transactions between a memory and the at least two processors;
at least one hub for input/output devices;
at least one bridge to send and receive transactions between the at least one hub for input/output devices and the at least two processors; and
at least two crossbars, each communicatively coupled to one of the at least two processors, to route the transactions between the at least one hub for input/output devices and the at least two processors;
wherein the at least two crossbars are each communicatively coupled to one of the at least two memory controllers to route transactions between the at least one hub for input/output devices and the memory.
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Abstract
A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
34 Citations
9 Claims
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1. A multiprocessor system comprising:
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at least two processors, each processor having at least one processing core; at least two memory controllers, each communicatively coupled to one of the at least two processors, to facilitate transactions between a memory and the at least two processors; at least one hub for input/output devices; at least one bridge to send and receive transactions between the at least one hub for input/output devices and the at least two processors; and at least two crossbars, each communicatively coupled to one of the at least two processors, to route the transactions between the at least one hub for input/output devices and the at least two processors; wherein the at least two crossbars are each communicatively coupled to one of the at least two memory controllers to route transactions between the at least one hub for input/output devices and the memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification