METHOD AND APPARATUS FOR ERROR CORRECTION ACCORDING TO ERASE COUNTS OF A SOLID-STATE MEMORY
First Claim
1. ) A method for handling error correction, the method comprisinga) maintaining an erase count for at least one block of a solid state memory;
- b) reading data from one of the memory blocks having an associated erase count;
c) in accordance with the associated erase count of the memory block, effecting at least one of;
i) choosing one of a first decoder and a second decoder; and
ii) choosing one of a first decoder mode and a second decoder mode;
d) correcting errors in the read data using only the chosen decoder or the chosen mode.
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Accused Products
Abstract
Embodiments of the present invention relate to methods and devices where an erase count is maintained for at least one block of solid state memory. Errors are corrected in data read from the solid state memory in accordance with the associated erase count of the memory block. In some embodiments, one or more of the following error-correction operations may be effected according to the associated erase count of a memory block from which the data is read: (i) a decoder and/or decoder mode is selected; (ii) a decision to attempt correcting errors using a lighter-weight weight decoder (mode) and/or heavier weight decoder (mode) and/or faster decoder (mode) and/or slower decoder (mode) is made; (iii) a mode transition and/or error correction attempt resource budget is determined; (iv) a number of soft bits is determined; and (v) a decoding bus width size is selected.
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Citations
21 Claims
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1. ) A method for handling error correction, the method comprising
a) maintaining an erase count for at least one block of a solid state memory; -
b) reading data from one of the memory blocks having an associated erase count; c) in accordance with the associated erase count of the memory block, effecting at least one of; i) choosing one of a first decoder and a second decoder; and ii) choosing one of a first decoder mode and a second decoder mode; d) correcting errors in the read data using only the chosen decoder or the chosen mode. - View Dependent Claims (2, 3, 4)
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5. ) A method for handling error correction, the method comprising
a) maintaining an erase count for at least one block of a solid state memory; -
b) reading data from one of the memory blocks having an associated erase count; c) in accordance with the associated erase count, effecting at least one of; i) deciding whether to; A) attempt to correct errors using a lighter-weight decoder or B) attempt to correct errors using only a heavier-weight decoder that is heavier than the lighter weight decoder; ii) deciding whether to; A) attempt to correct errors using a faster decoder or B) attempt to correct errors using only a slower decoder that is slower than the faster decoder; iii) deciding whether to; A) attempt to correct errors using a lighter-weight mode of a particular decoder or B) attempt to correct errors using only a heavier-weight mode of the particular decoder that is heavier than the lighter weight mode; and iv) deciding whether to; A) attempt to correct errors using a faster mode of a particular decoder or B) attempt to correct errors using only a slower mode of the particular decoder that is slower than the faster mode; and d) in accordance with at least one of the decidings, correcting errors in the read data. - View Dependent Claims (6)
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7. ) A method for handling error correction, the method comprising:
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a) maintaining an erase count for at least one block of a solid state memory; b) reading data from one of the memory blocks having an associated erase count; c) in accordance with the associated erase count, determining at least one of; i) a mode transition condition; and ii) an error correction attempt resource budget; d) making a first attempt to correct errors in the read data using a first set of error correction parameters; and e) in the event that the first attempt to correct errors is unsuccessful making a second attempt to correct errors in the read data using a second set of error correction parameters, the second attempt being contingent upon at least one of; i) a triggering of the mode transition condition by the first attempt; and ii) an exhausting of the resource budget by the first attempt. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. ) A method for handling error correction, the method comprising:
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a) maintaining an erase count for at least one block of a memory; b) reading data from one of the memory blocks having an associated erase count; c) in accordance with the associated erase count, effecting at least one of; i) determining a number of soft bits to be read for the data; and ii) selecting a decoding bus width size; and d) in the event that the number of soft bits is determined, reading the number of soft bits for the data; and e) attempting to correct errors in the data using at least one of; i) the selected decoding bus width size; and ii) the read soft bits. - View Dependent Claims (15, 16, 17)
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18. ) A data storage device comprising:
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a) a solid state memory; and b) a device controller operative to; i) maintain an erase count for at least one block of the solid state memory; ii) read data from one of the memory blocks having an associated erase count; iii) in accordance with the associated erase count of the memory block, effect at least one of; A) choosing one of a first decoder and a second decoder; and B) choosing one of a first decoder mode and a second decoder mode; and iv) correct errors in the read data using only the chosen decoder or the chosen mode.
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19. ) A data storage device comprising:
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a) a solid-state memory; and b) a controller operative to; i) maintain an erase count for at least one block of the solid-state memory; ii) read data from one of the memory blocks having an associated erase count; iii) in accordance with the associated erase count, effect at least one of; A) deciding whether to; I) attempt to correct errors using a lighter-weight decoder or II) attempt to correct errors using only a heavier-weight decoder that is heavier than the lighter weight decoder; B) deciding whether to; I) attempt to correct errors using a faster decoder or II) attempt to correct errors using only a slower decoder that is slower than the faster decoder; C) deciding whether to; I) attempt to correct errors using a lighter-weight mode of a particular decoder or II) attempt to correct errors using only a heavier-weight mode of the particular decoder that is heavier than the lighter weight mode; and D) deciding whether to; I) attempt to correct errors using a faster mode of a particular decoder or II) attempt to correct errors using only a slower mode of the particular decoder that is slower than the faster mode, iv) in accordance with at least one of the decidings, correct errors in the read data.
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20. ) A data storage device comprising:
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a) a solid state memory; and b) a device controller operative to; i) maintain an erase count for at least one block of the solid state memory; ii) read data from one of the memory blocks having an associated erase count; iii) in accordance with the associated erase count, determine at least one of; A) a mode transition condition; and B) an error correction attempt resource budget; iv) make a first attempt to correct errors in the read data using a first set of error correction parameters; and v) in the event that the first attempt to correct errors is unsuccessful, make a second attempt to correct errors in the read data using a second set of error correction parameters, the second attempt being contingent upon at least one of; A) a triggering of the mode transition condition by the first attempt; and B) an exhausting of the resource budget by the first attempt.
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21. ) A data storage device comprising:
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a) a solid state memory; and b) a device controller operative to; i) maintain an erase count for at least one block of the solid-state memory; ii) read data from one of the memory blocks having an associated erase count; iii) in accordance with the associated erase count, effect at least one of; A) determining a number of soft bits to be read for the data; and B) selecting a decoding bus width size; and iv) in the event that the number of soft bits is determined, read the number of soft bits for the data; and v) attempt to correct errors in the data using at least one of; A) the selected decoding bus width size; and B) the read soft bits.
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Specification