METHOD AND APPARATUS FOR ERROR CORRECTION ACCORDING TO ERASE COUNTS OF A SOLID-STATE MEMORY

• US 20090319859A1
• Filed: 05/06/2009
• Published: 12/24/2009
• Est. Priority Date: 06/24/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk IL Ltd. (Western Digital Corporation)
• Inventors: SHARON, Eran, ALROD, Idan, LASSER, Menahem
• Granted Patent: US 8,464,134 B2
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

Embodiments of the present invention relate to methods and devices where an erase count is maintained for at least one block of solid state memory. Errors are corrected in data read from the solid state memory in accordance with the associated erase count of the memory block. In some embodiments, one or more of the following error-correction operations may be effected according to the associated erase count of a memory block from which the data is read: (i) a decoder and/or decoder mode is selected; (ii) a decision to attempt correcting errors using a lighter-weight weight decoder (mode) and/or heavier weight decoder (mode) and/or faster decoder (mode) and/or slower decoder (mode) is made; (iii) a mode transition and/or error correction attempt resource budget is determined; (iv) a number of soft bits is determined; and (v) a decoding bus width size is selected.

Claims

1. ) A method for handling error correction, the method comprising

a) maintaining an erase count for at least one block of a solid state memory;

b) reading data from one of the memory blocks having an associated erase count;

c) in accordance with the associated erase count of the memory block, effecting at least one of;

i) choosing one of a first decoder and a second decoder; and

ii) choosing one of a first decoder mode and a second decoder mode;

d) correcting errors in the read data using only the chosen decoder or the chosen mode.

2. ) The method of claim 1 wherein the solid state memory is a flash memory.

3. ) The method of claim 1 wherein at least one of the maintaining, the reading, the effecting, and the correcting is carried out by a device controller of a storage device in which the solid state memory resides.

4. ) The method of claim 3 wherein the storage device is operatively coupled to a host device via an inter-device interface, and wherein the method further comprises:

e) sending the error-corrected data from the storage device to the host device.

5. ) A method for handling error correction, the method comprising

a) maintaining an erase count for at least one block of a solid state memory;

b) reading data from one of the memory blocks having an associated erase count;

c) in accordance with the associated erase count, effecting at least one of;

i) deciding whether to;

A) attempt to correct errors using a lighter-weight decoder or

B) attempt to correct errors using only a heavier-weight decoder that is heavier than the lighter weight decoder;

ii) deciding whether to;

A) attempt to correct errors using a faster decoder or

B) attempt to correct errors using only a slower decoder that is slower than the faster decoder;

iii) deciding whether to;

A) attempt to correct errors using a lighter-weight mode of a particular decoder or

B) attempt to correct errors using only a heavier-weight mode of the particular decoder that is heavier than the lighter weight mode; and

iv) deciding whether to;

A) attempt to correct errors using a faster mode of a particular decoder or

B) attempt to correct errors using only a slower mode of the particular decoder that is slower than the faster mode; and

d) in accordance with at least one of the decidings, correcting errors in the read data.

6. ) The method of claim 5 wherein at least one of the maintaining, the reading, one or more of the decidings, and the correcting is carried out by a device controller of a storage device in which the solid state memory resides.

7. ) A method for handling error correction, the method comprising:

a) maintaining an erase count for at least one block of a solid state memory;

b) reading data from one of the memory blocks having an associated erase count;

c) in accordance with the associated erase count, determining at least one of;

i) a mode transition condition; and

ii) an error correction attempt resource budget;

d) making a first attempt to correct errors in the read data using a first set of error correction parameters; and

e) in the event that the first attempt to correct errors is unsuccessful making a second attempt to correct errors in the read data using a second set of error correction parameters, the second attempt being contingent upon at least one of;

i) a triggering of the mode transition condition by the first attempt; and

ii) an exhausting of the resource budget by the first attempt.

8. ) The method of claim 7 wherein:

i) the method includes determining the mode transition condition; and

ii) the second attempt is contingent upon at least the triggering of the mode transition condition by the first attempt.

9. ) The method of claim 7 wherein:

i) the method includes determining the resource budget; and

ii) the second attempt is contingent upon at least the exhausting of the resource budget by the first attempt.

10. ) The method of claim 7 wherein at least one error correction parameter is selected from the group consisting of:

i) a selection parameter for selecting a decoder from a plurality of decoders;

ii) a decoder mode parameter for selecting a decoder mode for a given decoder from a plurality of decoder modes;

iii) a bit-probability value for the read data;

iv) a number of soft bits; and

v) a decoder bus width.

11. ) The method of claim 7 wherein the mode transition condition is selected from the group consisting of:

i) a timeout condition;

ii) a number of iterations condition; and

iii) a number of CPU cycles condition

12. ) The method of claim 7 wherein the error correction attempt resource budget is selected from the group consisting of:

i) a time budget;

ii) a CPU cycles budget; and

iii) an iterations budget.

13. ) The method of claim 7 wherein at least one of the maintaining, the reading, the determining, and one or more of the attempts is carried out by a device controller of a storage device in which the solid state memory resides.

14. ) A method for handling error correction, the method comprising:

a) maintaining an erase count for at least one block of a memory;

b) reading data from one of the memory blocks having an associated erase count;

c) in accordance with the associated erase count, effecting at least one of;

i) determining a number of soft bits to be read for the data; and

ii) selecting a decoding bus width size; and

d) in the event that the number of soft bits is determined, reading the number of soft bits for the data; and

e) attempting to correct errors in the data using at least one of;

i) the selected decoding bus width size; and

ii) the read soft bits.

15. ) The method of claim 14 wherein:

i) the method includes determining the number of soft bits to be read for the data and reading the number of soft bits for the data; and

ii) the attempting includes attempting to correct errors in the data using at least the read soft bits.

16. ) The method of claim 14 wherein:

i) the method includes selecting the decoding bus width size; and

ii) the attempting includes attempting to correct errors in the data using the selected decoding bus width size.

17. ) The method of claim 14 wherein at least one of the maintaining, one or more of the readings, the determining, the selecting and the attempting is carried out by a device controller of a storage device in which the solid state memory resides.

18. ) A data storage device comprising:

a) a solid state memory; and

b) a device controller operative to;

i) maintain an erase count for at least one block of the solid state memory;

ii) read data from one of the memory blocks having an associated erase count;

iii) in accordance with the associated erase count of the memory block, effect at least one of;

A) choosing one of a first decoder and a second decoder; and

B) choosing one of a first decoder mode and a second decoder mode; and

iv) correct errors in the read data using only the chosen decoder or the chosen mode.

19. ) A data storage device comprising:

a) a solid-state memory; and

b) a controller operative to;

i) maintain an erase count for at least one block of the solid-state memory;

ii) read data from one of the memory blocks having an associated erase count;

iii) in accordance with the associated erase count, effect at least one of;

A) deciding whether to;

I) attempt to correct errors using a lighter-weight decoder or

II) attempt to correct errors using only a heavier-weight decoder that is heavier than the lighter weight decoder;

B) deciding whether to;

I) attempt to correct errors using a faster decoder or

II) attempt to correct errors using only a slower decoder that is slower than the faster decoder;

C) deciding whether to;

I) attempt to correct errors using a lighter-weight mode of a particular decoder or

II) attempt to correct errors using only a heavier-weight mode of the particular decoder that is heavier than the lighter weight mode; and

D) deciding whether to;

I) attempt to correct errors using a faster mode of a particular decoder or

II) attempt to correct errors using only a slower mode of the particular decoder that is slower than the faster mode,

iv) in accordance with at least one of the decidings, correct errors in the read data.

20. ) A data storage device comprising:

a) a solid state memory; and

b) a device controller operative to;

i) maintain an erase count for at least one block of the solid state memory;

ii) read data from one of the memory blocks having an associated erase count;

iii) in accordance with the associated erase count, determine at least one of;

A) a mode transition condition; and

B) an error correction attempt resource budget;

iv) make a first attempt to correct errors in the read data using a first set of error correction parameters; and

v) in the event that the first attempt to correct errors is unsuccessful, make a second attempt to correct errors in the read data using a second set of error correction parameters, the second attempt being contingent upon at least one of;

A) a triggering of the mode transition condition by the first attempt; and

B) an exhausting of the resource budget by the first attempt.

21. ) A data storage device comprising:

a) a solid state memory; and

b) a device controller operative to;

i) maintain an erase count for at least one block of the solid-state memory;

ii) read data from one of the memory blocks having an associated erase count;

iii) in accordance with the associated erase count, effect at least one of;

A) determining a number of soft bits to be read for the data; and

B) selecting a decoding bus width size; and

iv) in the event that the number of soft bits is determined, read the number of soft bits for the data; and

v) attempt to correct errors in the data using at least one of;

A) the selected decoding bus width size; and

B) the read soft bits.