METHOD AND APPARATUS FOR DYNAMICALLY CONFIGURABLE MULTI LEVEL ERROR CORRECTION

• US 20090319864A1
• Filed: 06/20/2008
• Published: 12/24/2009
• Est. Priority Date: 06/20/2008
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Denali Software Incorporated (Cadence Group)
• Inventors: Shrader, Steven
• Granted Patent: US 8,627,169 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/3715 Adaptation to the number of estimated errors or to the channel state

Abstract

An invention is provided for dynamically configurable error correction. The invention includes receiving a check code configuration signal, which indicates a particular level of error detection. A check code generator is configured to generate check codes based on the particular level of error detection indicated by the check code configuration signal. In addition, an error locator configuration signal is received that indicates a particular level of error addressing, and an error locator is configured to produce addresses of errors in a set of data based on the particular level of error addressing indicated by the error locator configuration signal.

Claims

1. A method for providing dynamically configurable error correction, comprising the operations of:

receiving a check code configuration signal, wherein the check code configuration signal indicates a particular level of error detection;

configuring a check code generator to generate check codes based on the particular level of error detection indicated by the check code configuration signal;

receiving an error locator configuration signal, wherein the error locator configuration signal indicates a particular level of error addressing; and

configuring an error locator to produce addresses of errors in a set of data based on the particular level of error addressing indicated by the error locator configuration signal.

2. A method as recited in claim 1, wherein the check code configuration signal indicates a number of bits having errors that can be detected in data.

3. A method as recited in claim 1, wherein the check code generator generates an amount of error correction code (ECC) data based on the level of error detection indicated by the check code configuration signal.

4. A method as recited in claim 1, wherein the error locator configuration signal indicates a number of addresses of bits having errors in data that can be calculated by the error locator.

5. A method as recited in claim 1, wherein the error locator calculates a number of roots to a syndrome polynomial based on the level of error addressing indicated by the error locator configuration signal.

6. A method as recited in claim 1, wherein the error locator is configured to utilize a particular amount of existing error locator hardware based on the level of error addressing indicated by the error locator configuration signal.

7. A method as recited in claim 6, wherein the error locator utilizes an amount of error locator hardware less than a total amount of error locator hardware when the level of error addressing indicated by the error locator configuration signal is less than a maximum level of error addressing supported by the system.

8. A non-volatile memory controller having dynamically configurable multi level error correction, comprising:

a check code configuration signal indicating a particular level of error detection;

a check code generator coupled to the check code configuration signal, the check code generator being configured to generate an amount of error correction code (ECC) data based the particular level of error detection indicated by the check code configuration signal;

an error locator configuration signal indicating a particular level of error addressing; and

an error locator coupled to the error locator configuration signal, the error locator being configured to calculate addresses of errors in a set of data based on the particular level of error addressing indicated by the error locator configuration signal.

9. A non-volatile memory controller as recited in claim 8, wherein the check code generator is a read check code generator that calculates a syndrome polynomial based on read data received and the level or error detection indicated by the check code configuration signal.

10. A non-volatile memory controller as recited in claim 9, wherein the error locator configuration signal indicates a number of addresses of bits having errors in data that can be calculated by the error locator.

11. A non-volatile memory controller as recited in claim 10, wherein the error locator calculates a number of roots to the syndrome polynomial based on the level of error addressing indicated by the error locator configuration signal.

12. A non-volatile memory controller as recited in claim 9, further comprising a write check code generator coupled to the check code configuration signal, the write check code generator being configured to generate an amount of ECC data based the particular level of error detection indicated by the check code configuration signal.

13. A non-volatile memory controller as recited in claim 8, wherein the check code configuration signal indicates a number of bits having errors that can be detected in data.

14. A non-volatile memory controller as recited in claim 8, wherein the error locator is configured to utilize a particular amount of existing error locator hardware based on the level of error addressing indicated by the error locator configuration signal.

15. A non-volatile memory controller as recited in claim 14, wherein the error locator utilizes an amount of error locator hardware less than a total amount of error locator hardware when the level of error addressing indicated by the error locator configuration signal is less than a maximum level of error addressing supported by the system.

16. A method for providing dynamically configurable error correction, comprising the operations of:

receiving a check code configuration signal, wherein the check code configuration signal indicates a number of bits having errors that can be detected in data;

configuring a check code generator to generate check codes based on a value of the check code configuration signal;

receiving an error locator configuration signal, wherein the error locator configuration signal indicates a number of addresses of bits having errors in data that can be calculated by the error locator; and

configuring an error locator to produce addresses of errors in a set of data based on a value of the error locator configuration signal, wherein the error locator is configured to utilize a particular amount of existing error locator hardware based on the level of error addressing indicated by the error locator configuration signal.

17. A method as recited in claim 16, wherein the check code generator generates an amount of error correction code (ECC) data based on the value of the check code configuration signal.

18. A method as recited in claim 16, wherein the error locator calculates a number of roots to a syndrome polynomial based on the value of the error locator configuration signal.

19. A method as recited in claim 16, wherein the error locator utilizes an amount of error locator hardware less than a total amount of error locator hardware when the level of error addressing indicated by the error locator configuration signal is less than a maximum level of error addressing supported by the system.