Power state-aware thread scheduling mechanism

• US 20090320031A1
• Filed: 06/19/2008
• Published: 12/24/2009
• Est. Priority Date: 06/19/2008
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Song, Justin J.
• Application Number:
  US12/214,523
• Publication Number:
  US 20090320031A1
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 2209/501 Performance criteria
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system filter is maintained to track which single-thread cores [or which multi-threaded logical CPUs] are in a low-latency power state. For at least one embodiment, low-latency power states include an active C0 state and a low-latency C1 idle state. The system filter is used to filter out any cores/thread contexts in a high-latency state during task scheduling. This may be accomplished by filtering the OS-provided task affinity mask by the system filter. As a result, tasks are scheduled only on available cores/logical CPUs that are in an active or low-latency idle state. Other embodiments are described and claimed.

Claims

1. A method comprising:

based on power state information for each of a plurality of thread units, maintaining a system power state filter to indicate which of the thread units are in a low-latency power state; and

utilizing said system power state filter to schedule said task on one of the thread units that is in said low-latency power state.

2. The method of claim 1, wherein said utilizing further comprises:

filtering a task affinity mask, which represents the thread units available for scheduling of said task, to remove any of said thread units that are not in said low-latency power state.

3. The method of claim 2, wherein said low-latency power state further comprises an active state.

4. The method of claim 2, wherein said low-latency power state further comprises a core-clockgated idle state.

5. The method of claim 2, wherein said low-latency power state further comprises a state from the set of states comprising (a core-clockgated idle state and an active state).

6. The method of claim 1, wherein said plurality of thread units reside in the same die package.

7. The method of claim 1, wherein said plurality of thread units reside in a plurality of die packages of a processing system.

8. The method of claim 7, further comprising:

scheduling said task on one of the die packages that is in a low-latency package power state.

9. The method of claim 1, wherein said maintaining further comprises:

updating the system power state filter to indicate an “

unavailable”

state for any of the thread units entering a high-latency idle state.

10. The method of claim 1, wherein said maintaining further comprises:

updating the system power state filter to indicate an “

available”

state for any of the thread units that enters an active state.

11. The method of claim 1, wherein said maintaining further comprises:

updating the system power state filter to indicate an “

available”

state for any of the thread units that enters a low-latency idle state.

12. A system comprising:

a processor including a plurality of thread units;

a power management module to maintain an indicator to reflect whether each of the thread units is in a high-latency power state; and

a scheduler to select one of the thread units for a current task, based on the indicator;

wherein the scheduler is to decline to schedule the task on any of the cores that is in the high-latency power state.

13. The system of claim 12, further comprising:

a memory coupled to the processor.

14. The system of claim 13, wherein the memory is a DRAM.

15. The system of claim 13, wherein the memory is to store code for the scheduler.

16. The system of claim 13, wherein the memory is to store the power management module.

17. The system of claim 12, further comprising one or more additional processors.

18. The system of claim 12, wherein the processors reside on the same die package.

19. The system of claim 12, wherein the scheduler is to select one of the thread units for the current task, based on the indicator and a CPU availability indicator.

20. The system of claim 19, wherein the scheduler is to select one of the cores that is in the high-latency power state, responsive to determining that all cores indicated by the CPU availability indicator are in the high-latency state.

21. An article comprising a machine-accessible medium including instructions that when executed cause a system to:

receive power state information for a plurality of cores of a processor package;

determine which of the cores are available for scheduling of a task;

filter said availability to remove any of the cores that are in a high-latency power state to determine a set of cores having task affinity; and

schedule said task on one of the cores in the set.

22. The article of claim 21, further comprising instructions that when executed enable the system to perform said determining by consulting an operating-system provided default affinity value for the task.

23. The article of claim 21, wherein said power state information further comprises an indication of which of the cores are in the high-latency power state.

24. The article of claim 21, wherein the high-latency power state further comprises a deep core C-state.

25. The article of claim 21, wherein further comprising instructions that when executed enable the system to schedule said task on one of the cores in the high-latency power state, responsive to the set being empty.