THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME AND FLAT PANEL DISPLAY DEVICE HAVING THE SAME

• US 20090321731A1
• Filed: 01/13/2009
• Published: 12/31/2009
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: JEONG, Jae-Kyeong, Kim, Min-Kyu, Ahn, Tae-Kyung, Yang, Hui-Won, Mo, Yeon-Gon, Jeong, Jong-Han
• Granted Patent: US 8,148,779 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor (TFT) using an oxide semiconductor as an active layer, a method of manufacturing the TFT, and a flat panel display device having the TFT include a gate electrode formed on a substrate; an active layer made of an oxide semiconductor and insulated from the gate electrode by a gate insulating layer; source and drain electrodes coupled to the active layer; and an interfacial stability layer formed on one or both surfaces of the active layer. In the TFT, the interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0 eV. Since the interfacial stability layer has the same characteristic as a gate insulating layer and a passivation layer, chemically high interface stability is maintained. Since the interfacial stability layer has a band gap equal to or greater than that of the active layer, charge trapping is physically prevented.

Claims

1. A thin film transistor (TFT), comprising:

a substrate;

a gate electrode formed on the substrate;

a gate insulating layer formed on the substrate to cover the gate electrode;

an active layer formed of an oxide semiconductor and insulated from the gate electrode by the gate insulating layer;

source and drain electrodes electrically coupled to the active layer; and

an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer, the interfacial stability layer being formed of an oxide having a band gap of 3.0 to 8.0 eV.

2. The TFT of claim 1, wherein the oxide semiconductor comprises zinc oxide (ZnO).

3. The TFT of claim 2, wherein the oxide semiconductor is doped with at least one ion of gallium (Ga), indium (In), tin (Sn), zirconium (Zr), hafnium (Hf), cadmium (Cd), silver (Ag), copper (Cu), germanium (Ge), gadolinium (Gd), and vanadium (V).

4. The TFT of claim 1, further comprising:

a passivation layer formed on the substrate to cover the active layer, the passivation layer having contact holes formed therein so as to expose the active layer,

wherein the source and drain electrodes are electrically coupled to the active layer through the contact holes.

5. The TFT of claim 1, wherein sidewalls of the interfacial stability layer and the active layer correspond to each other.

6. The TFT of claim 1, wherein the interfacial stability layer is formed wider than the active layer when the interfacial stability layer is formed at the bottom surface of the active layer.

7. The TFT of claim 1, wherein the interfacial stability layer comprises one selected from the group consisting of SiO_x, SiN, SiO_xN_y, SiO_xC_y, SiO_xC_yH_z, SiO_xF_y, GeO_x, GdO_x, AlO_x, GaO_x, SbO, ZrO_x, HfO_x, TaO_x, YO_x, VO_x, MgO_x, CaO_x, BaO_x, SrO_x, and spin on glass (SOG).

8. The TFT of claim 1, wherein an oxygen concentration of the interfacial stability layer is 10¹⁹/cm³ or lower.

9. A method of manufacturing a TFT, comprising:

forming agate electrode on a substrate;

forming a gate insulating layer on the substrate to cover the gate electrode;

sequentially forming a first interfacial stability layer and an oxide semiconductor layer on the gate insulating layer;

patterning the oxide semiconductor layer to form an active layer; and

forming source and drain electrodes electrically coupled to the active layer,

wherein the first interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0 eV.

10. The method of claim 9, wherein the first interfacial stability layer comprises one selected from the group consisting of SiO_x, SiN, SiO_xN_y, SiO_xC_y, SiO_xC_yH_z, SiO_xF_y, GeO_x, GdO_x, AlO_x, GaO_x, SbO, ZrO_x, HfO_x, TaO_x, YO_x, VO_x, MgO_x, CaO_x, BaO_x, SrO_x, and SOG.

11. The method of claim 10, wherein the first interfacial stability layer is formed using a physical deposition method.

12. The method of claim 9, wherein the oxide semiconductor layer comprises zinc oxide (ZnO).

13. The method of claim 12, wherein the oxide semiconductor layer is doped with at least one ion of gallium (Ga), indium (In), tin (Sn), zirconium (Zr), hafnium (Hf), cadmium (Cd), silver (Ag), copper (Cu), germanium (Ge), gadolinium (Gd), and vanadium (V).

14. The method of claim 9, wherein the first interfacial stability layer is patterned in the forming the active layer.

15. The method of claim 9, further comprising forming a second interfacial stability layer on the active layer opposite the first interfacial stability layer.

16. The method of claim 15, wherein the second interfacial stability layer is formed to a thickness of 10 to 20 Å

.

17. The method of claim 9, wherein the first interfacial stability layer is formed to a thickness of 50 to 5000 Å

.

18. The method of claim 15, wherein the second interfacial stability layer comprises one selected from the group consisting of SiO_x, SiN, SiO_xN_y, SiO_xC_y, SiO_xC_yH_z, SiO_xF_y, GeO_x, GdO_x, AlO_x, GaO_x, SbO, ZrO_x, HfO_x, TaO_x, YO_x, VO_x, MgO_x, CaO_x, BaO_x, SrO_x, and SOG.

19. The method of claim 18, wherein the second interfacial stability layer is formed using a physical deposition method.

20. The method of claim 9, further comprising:

forming a passivation layer on the substrate having the active layer;

forming contact holes in the passivation layer so to expose the active layer;

forming a conductive layer on the passivation layer to fill the contact holes; and

patterning the conductive layer to form source and drain electrodes.

21. The method of claim 20, wherein the passivation layer is formed of an oxide including a material selected from the group consisting of zinc (Zn), gallium (Ga), indium (In), tin (Sn), zirconium (Zr), hafnium (Hf), cadmium (Cd), silver (Ag), copper (Cu), germanium (Ge), gadolinium (Gd), vanadium (V), silicon (Si), and aluminum (Al).

22. The method of claim 20, wherein the passivation layer is used as an etch stop layer when the conductive layer is patterned.

23. A method of manufacturing a TFT, comprising:

forming agate electrode on a substrate;

forming a gate insulating layer on the substrate having the gate electrode;

sequentially forming an oxide semiconductor layer and an interfacial stability layer on the gate insulating layer;

patterning the interfacial stability layer and the oxide semiconductor layer to form an active layer; and

forming source and drain electrodes electrically coupled to the active layer,

wherein the interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0 eV.

24. The method of claim 23, wherein the oxide semiconductor layer comprises zinc oxide (ZnO).

25. The method of claim 24, wherein the oxide semiconductor layer is doped with at least one ion of gallium (Ga), indium (In), tin (Sn), zirconium (Zr), hafnium (Hf), cadmium (Cd), silver (Ag), copper (Cu), germanium (Ge), gadolinium (Gd), and vanadium (V).

26. The method of claim 23, wherein the interfacial stability layer comprises one selected from the group consisting of SiO_x, SiN, SiO_xN_y, SiO_xC_y, SiO_xC_yH_z, SiO_xF_y, GeO_x, GdO_x, AlO_x, GaO_x, SbO, ZrO_x, HfO_x, TaO_x, YO_x, VO_x, MgO_x, CaO_x, BaO_x, SrO_x, and SOG.

27. The method of claim 23, wherein the interfacial stability layer is formed using a physical deposition method.

28. The method of claim 23, wherein the interfacial stability layer is formed to a thickness of 10 to 20 Å

.

29. A flat panel display device, comprising:

a first substrate having disposed thereon;

a plurality of pixels, each of the plurality of pixels having a first electrode, and

a plurality of thin film transistors,

wherein the pixels are defined by a plurality of first and second conductive lines, the thin film transistors control signals supplied to the respective pixels, and the first electrodes are respectively coupled to the thin film transistors;

a second substrate having a second electrode formed thereon; and

a liquid crystal layer disposed in a space sealed between the first and second electrodes,

wherein each of the thin film transistors comprises;

a gate electrode formed on the first substrate and electrically connected one of the first and second conductive lines;

a gate insulating layer formed on the first substrate to cover the gate electrode;

an active layer made of an oxide semiconductor and insulated from the gate electrode by the gate insulating layer;

source and drain electrodes electrically coupled to the active layer, one of the source and drain electrodes electrically coupled to the other of the first and second conductive lines, and the other of the source and drain electrodes electrically coupled to the first electrode; and

an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer,

wherein the interfacial stability layer has a band gap of 3.0 to 8.0 eV.

30. The flat panel display device of claim 29, wherein the oxide semiconductor comprises zinc oxide (ZnO).

31. The flat panel display device of claim 30, wherein the oxide semiconductor is doped with at least one ion of gallium (Ga), indium (In), tin (Sn), zirconium (Zr), hafnium (Hf), cadmium (Cd), silver (Ag), copper (Cu), germanium (Ge), gadolinium (Gd), and vanadium (V).

32. The flat panel display device of claim 29, wherein each of the thin film transistors further comprises a passivation layer formed on the substrate to cover the active layer, the passivation layer having contact holes formed therein so as to expose the active layer,

wherein the source and drain electrodes are coupled to the active layer through the contact holes.

33. The flat panel display device of claim 29, wherein the interfacial stability layer is formed wider than the active layer.

34. The flat panel display device of claim 29, wherein the interfacial stability layer comprises one selected from the group consisting of SiO_x, SiN, SiO_xN_y, SiO_xC_y, SiO_xC_yH_z, SiO_xF_y, GeO_x, GdO_x, AlO_x, GaO_x, SbO, ZrO_x, HfO_x, TaO_x, YO_x, VO_x, MgO_x, CaO_x, BaO_x, SrO_x, and SOG.

35. A flat panel display device, comprising:

a first substrate having an organic light emitting device, scan and data lines, and a thin film transistor formed thereon, the organic light emitting device including a first electrode, an organic thin film layer, and a second electrode, and the thin film transistor controlling operation of the organic light emitting device; and

a second substrate disposed opposite to the first substrate,

wherein the thin film transistor comprises;

a gate electrode formed on the first substrate electrically coupled to one of the scan and data lines;

a gate insulating layer formed on the first substrate to cover the gate electrode;

an active layer made of an oxide semiconductor and insulated from the gate electrode by the gate insulating layer;

source and drain electrodes coupled to the active layer, one of the source and drain electrodes electrically coupled to the other of the scan and data lines, and the other of the source and drain electrodes electrically coupled to the first electrode; and

an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer,

wherein the interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0 eV.

36. The flat panel display device of claim 35, wherein the oxide semiconductor comprises zinc oxide (ZnO).

37. The flat panel display device of claim 36, wherein the oxide semiconductor is doped with at least one ion of gallium (Ga), indium (In), tin (Sn), zirconium (Zr), hafnium (Hf), cadmium (Cd), silver (Ag), copper (Cu), germanium (Ge), gadolinium (Gd), and vanadium (V).

38. The flat panel display device of claim 35, further comprising a passivation layer formed on the substrate to cover the active layer, the passivation layer having contact holes formed therein so as to expose the active layer,

wherein the source and drain electrodes are coupled to the active layer through the contact holes.

39. The flat panel display device of claim 35, wherein the interfacial stability layer is formed wider than the active layer.

40. The flat panel display device of claim 35, wherein the interfacial stability layer comprises one selected from the group consisting of SiO_x, SiN, SiO_xN_y, SiO_xC_y, SiO_xC_yH_z, SiO_xF_y, GeO_x, GdO_x, AlO_x, GaO_x, SbO, ZrO_x, HfO_x, TaO_x, YO_x, VO_x, MgO_x, CaO_x, BaO_x, SrO_x, and SOG.

41. A thin film transistor (TFT), comprising:

a substrate;

a gate electrode formed on the substrate;

a gate insulating layer formed on the substrate to cover the gate electrode;

an active layer formed of an oxide semiconductor and insulated from the gate electrode by the gate insulating layer;

source and drain electrodes electrically coupled to the active layer; and

an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer, the interfacial stability layer being formed of an oxide having a band gap equal to or greater than a band gap of the active layer.

42. A thin film transistor (TFT), comprising:

a substrate;

a gate electrode formed on the substrate;

a gate insulating layer formed on the substrate to cover the gate electrode;

an active layer formed of an oxide semiconductor and insulated from the gate electrode by the gate insulating layer;

source and drain electrodes electrically coupled to the active layer; and

an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer, an oxygen concentration of the interfacial stability layer being 10¹⁹/cm³ or lower.