Triangle two dimensional complementary patterning of pillars

• US 20090321789A1
• Filed: 06/30/2008
• Published: 12/31/2009
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Wang, Chun-Ming, Chen, Yung-Tin
• Granted Patent: US 7,781,269 B2
• Time in Patent Office: Days
• US Class Current: 257/202
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device. The plurality of pillars include a plurality of first pillars having a first shape and a plurality of second pillars having a second shape different from the first shape.

Claims

1. A method of making a device, comprising:

forming at least one device layer over a substrate;

forming a plurality of spaced apart first features over the device layer, wherein each three adjacent first features form an equilateral triangle;

forming sidewall spacers on the first features;

filling a space between the sidewall spacers with a plurality of filler features;

selectively removing the sidewall spacers; and

etching the at least one device layer using at least the plurality of filler features as a mask.

2. A method of claim 1, wherein:

the step of selectively removing the sidewall spacers leaves the first features and the filler features spaced apart from each other; and

the step of etching the at least one device layer comprises etching the at least one device layer using the first features and the filler features as a mask.

3. A method of claim 1, further comprising selectively removing the first features after the step of forming sidewall spacers and before the step of filling a space between the sidewall spacers with a plurality of filler features.

4. A method of claim 3, wherein:

the step of selectively removing the sidewall spacers leaves the plurality of filler features spaced apart from each other; and

the step of etching the at least one device layer comprises etching the at least one device layer using the plurality of filler features as a mask.

5. A method of claim 1, wherein the step of etching the at least one device layer forms a plurality of first pillars having a first shape and a plurality second pillars having a second shape same or different from the first shape.

6. A method of claim 1, further comprising:

forming a plurality of rail-shaped bottom electrodes underneath the device layer.

7. A method of claim 6, wherein:

each three adjacent first features are formed over three adjacent bottom electrodes; and

each first feature of the three adjacent first features is located over a different bottom electrode.

8. A method of claim 7, further comprising forming a plurality of rail-shaped upper electrodes over the etched device layer, wherein the upper electrodes and the bottom electrodes extend in directions which differ from each other by about 60 degrees.

9. A method of claim 7, wherein:

the step of etching the at least one device layer forms a pattern comprising first pillars and second pillars, wherein the first pillars have a circular cross section and the second pillars have a cross section of a triangle with rounded corners;

a unit of three pillars comprising one first pillar and two second pillars repeats along a same bottom electrode;

three adjacent first pillars form an equilateral triangle;

six second pillars surround each first pillar in a hexagonal configuration; and

three first pillars surround each second pillar in an equilateral triangle configuration.

10. A method of claim 6, wherein:

two of each three adjacent first features are formed over one first bottom electrode;

a third feature of said three adjacent first features is formed over a third bottom electrode such that a second bottom electrode is adjacent to and located between the first bottom electrode and the third bottom electrode.

11. A method of claim 10, further comprising forming a plurality of rail-shaped upper electrodes over the device layer, wherein the upper electrodes extend perpendicular to the bottom electrodes.

12. A method of claim 10, wherein:

the step of etching the at least one device layer forms a pattern comprising first pillars and second pillars, wherein the first pillars have a circular cross section and the second pillars have a cross section of a triangle with rounded corners;

the first pillars are located over first bottom electrodes with a first distance between each two adjacent first pillars;

the second pillars are located over second bottom electrodes with a second distance between each two adjacent second pillars such that the second distance is shorter than the first distance;

the three adjacent first pillars form an equilateral triangle;

six of the second pillars surround each first pillar in a hexagonal configuration; and

three of the first type pillars surround each second pillar in a equilateral triangle configuration.

13. A method of claim 1, wherein the sidewalls spacers on adjacent first features along at least two predetermined directions contact each other to form fully enclosed interstitial spaces located between the sidewall spacers, and the filler features fill the interstitial spaces.

14. A method of claim 1, wherein:

the device comprises a plurality of nonvolatile memory cells; and

each the nonvolatile memory cell comprises a pillar diode as a steering element and a storage element.

15. A method of claim 14, the nonvolatile memory cell type is selected from at least one of antifuse, fuse, diode and antifuse arranged in a series, polysilicon memory effect cell, metal oxide memory, switchable complex metal oxide, carbon nanotube memory, graphene or carbon switchable resistance material, phase change material memory, conductive bridge element, or switchable polymer memory.

16. A method of making a pillar shaped nonvolatile memory device array, comprising:

forming a plurality of bottom electrodes over a substrate;

forming at least one semiconductor device layer over the plurality of bottom electrodes;

forming a plurality of spaced apart first features over the at least one semiconductor device layer, wherein each three adjacent first features form an equilateral triangle;

forming sidewall spacers on the plurality of spaced apart first features;

forming a filler film over and between the plurality of spaced apart first features;

planarizing the filler film to expose upper portions of the plurality of spaced apart first features and upper portions of the sidewall spacers to leave a plurality of filler features located between the sidewall spacers;

selectively removing the sidewall spacers;

etching the at least one semiconductor device layer to form a plurality of pillar-shaped diode containing nonvolatile memory cells using at least the plurality of filler features as a mask; and

forming a plurality of upper electrodes contacting the plurality of nonvolatile memory cells.

17. A method of claim 16, wherein:

the step of selectively removing sidewall spacers leaves the first features and filler features spaced apart from each other; and

the step of etching the at least one semiconductor device layer comprises etching the at least one semiconductor device layer using the plurality of first features and the plurality of filler features as a mask.

18. A method of claim 16, further comprising selectively removing the first features after the step of forming sidewall spacers, and before the step of forming a filler film.

19. A method of claim 18, wherein:

the step of selectively removing the sidewall spacers leaves the plurality of filler features spaced apart from each other; and

the step of etching at least one semiconductor device layer comprises etching the at least one semiconductor device layer using the plurality of filler features as a mask.

20. A method of claim 16, wherein:

each three adjacent first features are formed over three adjacent bottom electrodes; and

each first feature of the three adjacent first features is located over a different bottom electrode; and

the upper electrodes and the bottom electrodes extend in directions which differ from each other by about 60 degrees.

21. A method of claim 16, wherein:

two of each three adjacent first features are formed over one first bottom electrode;

the third first feature of said three adjacent first features is formed over a third bottom electrode such that a second bottom electrode is adjacent to and located between the first bottom electrode and the third bottom electrode; and

the upper electrodes extend perpendicular to the bottom electrodes.

22. A device, comprising:

a plurality of bottom electrodes located over a substrate;

a plurality of spaced apart pillars located over the plurality of bottom electrodes; and

a plurality of upper electrodes contacting the plurality of pillars;

wherein;

each three adjacent pillars form an equilateral triangle;

each pillar comprises a semiconductor device; and

the plurality of pillars comprise a plurality of first pillars having a first shape and a plurality of second pillars having a second shape different from the first shape.

23. A device of claim 22, wherein:

three adjacent first pillars form the equilateral triangle;

six second pillars surround each first pillar in a hexagonal configuration; and

three first pillars surround each second pillar in an equilateral triangle configuration.

24. A device of claim 23, wherein:

each three adjacent first pillars are located over three adjacent bottom electrodes;

each first pillar of the three adjacent first pillars is located over a different bottom electrode;

the upper electrodes and the bottom electrodes extend in directions which differ from each other by about 60 degrees; and

a unit of three pillars comprising one first pillar and two second pillars repeats along same bottom electrode.

25. A device of claim 23, wherein:

two of each three adjacent first pillars are located over one first bottom electrode;

a third pillar of said three adjacent first pillars is located over a third bottom electrode such that a second bottom electrode is adjacent to and located between the first bottom electrode and the third bottom electrode;

the upper electrodes extend perpendicular to the bottom electrodes;

the first pillars are located over the first bottom electrodes with a first distance between each two adjacent first pillars; and

the second pillars are located over the second bottom electrodes with a second distance between each two adjacent second pillars such that the second distance is shorter than the first distance.

26. A device of claim 23, wherein the first pillars have a circular cross section and the second pillars have a cross section of a triangle with rounded corners.

27. A device of claim 22, wherein each pillar comprises a semiconductor diode steering element and a nonvolatile memory storage element.