VERTICAL PROFILE FinFET GATE FORMED VIA PLATING UPON A THIN GATE DIELECTRIC

• US 20090321833A1
• Filed: 06/25/2008
• Published: 12/31/2009
• Est. Priority Date: 06/25/2008
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Koburger, Charles W. III, Furukawa, Toshiharu, Horak, David V., Deligianni, Hariklia, Holmes, Steven J., Basker, Veeraraghaven S.
• Application Number:
  US12/145,616
• Publication Number:
  US 20090321833A1
• Time in Patent Office: Days
• US Class Current: 257/365
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Methods of making vertical profile FinFET gate electrodes via plating upon a thin gate dielectric are disclosed. In one embodiment, a method for forming a transistor, comprises: providing a semiconductor topography comprising a semiconductor substrate and a semiconductor fin structure extending above the substrate; forming a gate dielectric across exposed surfaces of the semiconductor topography; patterning a mask upon the semiconductor topography such that only a select portion of the gate dielectric is exposed that defines where a gate electrode is to be formed; and plating a metallic material upon the select portion of the gate dielectric to form a gate electrode across a portion of the fin structure.

Claims

1. A method for forming a transistor, comprising:

providing a semiconductor topography comprising a semiconductor substrate and a semiconductor fin structure extending above the substrate;

forming a gate dielectric across exposed surfaces of the semiconductor topography;

patterning a mask upon the semiconductor topography such that only a select portion of the gate dielectric is exposed that defines where a gate electrode is to be formed; and

electroplating a metallic material upon the select portion of the gate dielectric to form a gate electrode across a portion of the fin structure.

2. The method of claim 1, wherein the gate dielectric has a thickness effective to allow the electroplating thereon.

3. The method of claim 2, wherein the thickness of the gate dielectric is about 0.7 nanometers to about 3.5 nanometers.

4. The method of claim 1, wherein the semiconductor topography further comprises a second semiconductor fin structure laterally spaced from the semiconductor fin structure, and wherein said electroplating also forms the gate electrode across a portion of the second fin structure.

5. The method of claim 1, further comprising, prior to said forming the gate dielectric, forming dielectric spacers upon sidewall surfaces of the semiconductor fin structure and then thermally growing silicon dioxide upon the semiconductor substrate to a thickness sufficient to prevent the substrate from being plated.

6. The method of claim 5, wherein the thickness of the silicon dioxide is about 6 nanometers to about 200 nanometers.

7. The method of claim 5, further comprising removing the dielectric spacers subsequent to said thermally growing the silicon dioxide.

8. The method of claim 1, wherein the gate dielectric comprises silicon dioxide, and further comprising, subsequent to said electroplating, removing the mask followed by selectively depositing an oxide by liquid phase deposition upon the gate dielectric residing on the semiconductor substrate and the fin structure.

9. The method of claim 8, wherein a thickness of the liquid phase deposition oxide is about 2 nanometers to about 10 nanometers.

10. The method of claim 8, further comprising additionally electroplating surfaces of the gate electrode to form metallic spacers over portions of the fin structure while the liquid phase deposition oxide protects the semiconductor substrate and the fin structure from being plated.

11. The method of claim 10, further comprising implanting regions of the fin structure not protected by the metallic spacers to form source and drain junctions.

12. The method of claim 1, wherein the mask comprises a photoresist mold having a slot for defining the gate electrode.

13-20. -20. (canceled)