CMOS DEVICE COMPRISING MOS TRANSISTORS WITH RECESSED DRAIN AND SOURCE AREAS AND A SI/GE MATERIAL IN THE DRAIN AND SOURCE AREAS OF THE PMOS TRANSISTOR

• US 20090321843A1
• Filed: 05/12/2009
• Published: 12/31/2009
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Grasshoff, Gunter, Wei, Andy, Waite, Andrew
• Granted Patent: US 7,723,174 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

The present disclosure relates to semiconductor devices and a process sequence in which a semiconductor alloy, such as silicon/germanium, may be formed in an early manufacturing stage, wherein other performance-increasing mechanisms, such as a recessed drain and source configuration, possibly in combination with high-k dielectrics and metal gates, may be incorporated in an efficient manner while still maintaining a high degree of compatibility with conventional process techniques.

Claims

1. A semiconductor device, comprising:

a transistor formed above a substrate and comprising drain and source regions comprising a strain-inducing semiconductor alloy, said drain and source regions further comprising metal silicide regions having a recessed surface portion that is positioned at a lower height level compared to a height level defined by a surface of a gate insulation layer separating a gate electrode from a channel region of said transistor; and

a strain-inducing layer formed above said drain and source regions, said strain-inducing layer and said strain-inducing semiconductor alloy inducing the same type of strain in said channel region.

2. The semiconductor device of claim 1, further comprising a sidewall spacer structure formed on sidewalls of said gate electrode and extending above a top surface of said gate electrode.

3. The semiconductor device of claim 1, further comprising a second transistor formed above said substrate and comprising second drain and source regions including second metal silicide regions having a recessed surface portion that is positioned at a lower height level compared to a height level defined by a surface of a gate insulation layer separating a second gate electrode from a second channel region of said second transistor, wherein said semiconductor device further comprises a second strain-inducing layer formed above said second drain and source regions and wherein said second strain-inducing layer induces a second type of strain in said second channel region that differs from said type of strain induced in said channel region.

4. The semiconductor device of claim 1, further comprising a metal silicide material formed in said gate electrode.

5. The semiconductor device of claim 1, wherein said gate insulation layer comprises a high-k dielectric material.

6. The semiconductor device of claim 5, wherein said gate electrode comprises a metal-containing material that is in contact with said high-k dielectric material.

7. The semiconductor device of claim 6, further comprising a dielectric material formed on said strain-inducing layer and on said metal-containing material of said gate electrode.

8. The semiconductor device of claim 6, wherein said strain-inducing layer is formed on said metal-containing material of said gate electrode.

9. The semiconductor device of claim 1, wherein said transistor is a P-channel transistor.

10. The semiconductor device of claim 3, wherein said transistor is a P-channel transistor and said second transistor is an N-channel transistor.

11. A method, comprising:

forming a gate electrode structure above a silicon-containing semiconductor region, said gate electrode structure comprising a cap layer, a first etch stop layer located below said cap layer and a second etch stop layer located below said first etch stop layer;

forming a strain-inducing semiconductor alloy in recesses in said silicon-containing semiconductor region laterally offset from said gate electrode structure;

forming drain and source regions in said semiconductor region and said semiconductor alloy;

removing material of said silicon-containing semiconductor region and said gate electrode structure so as to recess said drain and source regions by using said second etch stop layer as an etch stop; and

forming a strain-inducing layer above said drain and source regions.

12. The method of claim 11, wherein forming said strain-inducing semiconductor alloy comprises forming a spacer element on sidewalls of said gate electrode structure, forming said recesses in the presence of said spacer element and removing said spacer element and said cap layer after forming said strain-inducing semiconductor alloy in a common etch process.

13. The method of claim 11, further comprising forming a gate insulation layer of said gate electrode structure on the basis of a high-k dielectric material.

14. The method of claim 11, wherein forming said gate electrode structure comprises forming at least one of said first and second etch stop layers on the basis of a high-k dielectric material.

15. The method of claim 11, further comprising forming a metal-containing material in said gate electrode structure prior to forming said strain-inducing layer.

16. The method of claim 11, further comprising forming a metal-containing material in said gate electrode structure after forming said strain-inducing layer.

17. The method of claim 16, further comprising forming metal silicide regions in said drain and source regions and using said second etch stop layer as a mask layer.

18. The method of claim 17, wherein forming said metal-containing material in said gate electrode structure comprises removing material of said strain-inducing layer so as to expose a gate electrode material and replacing said gate electrode material with said metal-containing material.

19. The method of claim 18, further comprising forming a further strain-inducing material above said metal-containing material of said gate electrode structure.

20. A method, comprising:

forming drain and source regions of a first transistor in a semiconductor layer adjacent to a first gate electrode having formed on sidewalls thereof a first spacer structure, said drain and source regions of said first transistor comprising a strain-inducing semiconductor alloy;

forming drain and source regions of a second transistor adjacent to a second gate electrode having formed on sidewalls thereof a second spacer structure;

forming recesses in the drain and source regions of said first and second transistors and removing a portion of said first and second gate electrodes in a common etch process; and

forming a first strain-inducing material above the drain and source regions of said first transistor and forming a second strain-inducing material above the drain and source regions of said second transistor, said first and second strain-inducing materials generating a different type of strain.

21. The method of claim 20, further comprising replacing said first gate electrode by a first metal-containing electrode material and replacing said second gate electrode by a second metal-containing electrode material, wherein said first and second metal-containing electrode materials have different work functions.

22. The method of claim 21, further comprising forming a gate insulation layer of said first and second transistors on the basis of a high-k dielectric material.

23. The method of claim 22, further comprising forming a plurality of dielectric layers in said first and second gate electrodes.

24. The method of claim 23, wherein at least one of said plurality of dielectric layers is formed on the basis of a high-k dielectric material.

25. The method of claim 20, further comprising forming metal silicide regions in said drain and source regions of the first and second transistors and in said first and second gate electrodes in a common process.