SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
First Claim
1. A semiconductor device comprising:
- a semiconductor region;
a first electrode;
a second electrode;
a first terminal electrically connected to the first electrode; and
a second terminal electrically connected to the second electrode,wherein the first terminal is provided over the semiconductor region,wherein the semiconductor region includes;
a first impurity region having one of n-type and p-type conductivity;
a resistance region provided at an inner periphery portion of the first impurity region in a plane view; and
a second impurity region having the other of n-type and p-type conductivity which is provided at an inner periphery portion of the resistance region in the plane view,wherein the first impurity region is electrically connected to the first electrode, andwherein the second impurity region is electrically connected to the second electrode.
1 Assignment
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Accused Products
Abstract
A semiconductor device has a structure including the first semiconductor region 103 which is provided in the first terminal portion 100 and includes the first n-type impurity region 106, the first resistance region 107 provided at an inner periphery portion of the first n-type impurity region 106 in a plane view, and the first p-type impurity region 108 provided at an inner periphery portion of the first resistance region 107 in the plane view, and the second semiconductor region 104 which is provided in the second terminal portion 101 and includes the second p-type impurity region 109, the second resistance region 110 provided at an inner periphery portion of the second p-type impurity region 109 in the plane view, and the second n-type impurity region 111 provided at an inner periphery portion of the second resistance region 110 in the plane view.
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Citations
20 Claims
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1. A semiconductor device comprising:
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a semiconductor region; a first electrode; a second electrode; a first terminal electrically connected to the first electrode; and a second terminal electrically connected to the second electrode, wherein the first terminal is provided over the semiconductor region, wherein the semiconductor region includes; a first impurity region having one of n-type and p-type conductivity; a resistance region provided at an inner periphery portion of the first impurity region in a plane view; and a second impurity region having the other of n-type and p-type conductivity which is provided at an inner periphery portion of the resistance region in the plane view, wherein the first impurity region is electrically connected to the first electrode, and wherein the second impurity region is electrically connected to the second electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor device comprising:
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a semiconductor region; a first electrode; a second electrode; a first terminal electrically connected to the first electrode; and a second terminal electrically connected to the second electrode, wherein the second terminal is provided over the semiconductor region, wherein the semiconductor region includes; a first impurity region having one of n-type and p-type conductivity; a resistance region provided at an inner periphery portion of the first impurity region in a plane view; and a second impurity region having the other of n-type and p-type conductivity which is provided at an inner periphery portion of the resistance region in the plane view, wherein the first impurity region is electrically connected to the first electrode, and wherein the second impurity region is electrically connected to the second electrode. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A semiconductor device comprising:
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a first semiconductor region; a second semiconductor region; a first electrode; a second electrode; a third electrode; a fourth electrode; a first terminal electrically connected to the second electrode and the third electrode; and a second terminal electrically connected to the first electrode and the fourth electrode, wherein the first terminal is provided over the first semiconductor region, wherein the second terminal is provided over the second semiconductor region, wherein the first semiconductor region includes; a first n-type impurity region in contact with the first electrode; a first resistance region provided at an inner periphery portion of the first n-type impurity region in a plane view; and a first p-type impurity region which is provided at an inner periphery portion of the first resistance region in the plane view and is in contact with the second electrode, and wherein the second semiconductor region includes; a second p-type impurity region in contact with the third electrode; a second resistance region provided at an inner periphery portion of the second p-type impurity region in the plane view; and a second n-type impurity region which is provided at an inner periphery portion of the second resistance region in the plane view and is in contact with the fourth electrode. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification