ALIGNMENT FOR BACKSIDE ILLUMINATION SENSOR

• US 20090321888A1
• Filed: 09/03/2009
• Published: 12/31/2009
• Est. Priority Date: 12/06/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wuu, Shou-Gwo, Yaung, Dun-Nian, Liu, Jen-Cheng
• Granted Patent: US 8,227,899 B2
• Time in Patent Office: Days
• US Class Current: 257/618
• CPC Class Codes: H01L 21/71 Manufacture of specific parts of devices defined in group H01L21/70 H01L21/0405, H01L21/0445 , H01L21/28, H01L21/44, H01L21/48 take precedence
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2223/5446 Located in scribe lines
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.

Claims

1. An apparatus, comprising:

an integrated circuit located in a first region of a substrate having first and second opposing major surfaces; and

an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.

2. The apparatus of claim 1 wherein the alignment mark protrudes from one of the first and second surfaces.

3. The apparatus of claim 1 wherein the alignment mark protrudes from each of the first and second surfaces.

4. The apparatus of claim 1 wherein the alignment mark comprises a plurality of alignment marks each extending through the substrate between the first and second surfaces.

5. The apparatus of claim 1 wherein the second region interposes the first region and a perimeter of the substrate.

6. The apparatus of claim 1 wherein the second region, but not the first region, comprises a scribe region.

7. An a apparatus, comprising:

a first substrate having first and second opposing major surfaces, the first substrate including;

at least one transistors located in a first region of the first surface, and

at least one recess located in a second region of the first surface, wherein the at least one recess is filled with a material; and

a second substrate coupled to the first substrate such that the first surface of the first substrate is closer to the second substrate relative to the second surface of the first substrate;

wherein the material in the at least one recess is exposed through the second surface of the first substrate.

8. The apparatus of claim 7 wherein the material acts as an alignment mark.

9. The apparatus of claim 7 wherein the material substantially comprises a metallic composition.

10. The apparatus of claim 7 further comprising an isolation layer formed in the recess prior to filling the recess with the material.

11. The apparatus of claim 7 wherein the material has a higher resistance to chemical-mechanical planarizing relative to a bulk portion of one of the first and second substrates.

12. The apparatus of claim 7 wherein the second region, but not the first region, comprises a scribe region.

13. The apparatus of claim 7 wherein the material is coplanar with the second surface of the first substrate.

14. The apparatus of claim 7 wherein the material extends beyond the second surface of the first substrate.

15. An apparatus, comprising:

a first semiconductor substrate having a frontside surface and a backside surface;

a first layer formed over the frontside surface of the first semiconductor substrate;

a first recess formed through the first layer and extending into the first substrate to a first depth;

wherein the first recess is filled with a material;

a second recess formed through the first layer and extending into the first substrate to a second depth, wherein the second depth is substantially less than the first depth, wherein the second recess is filled with the material;

a second layer formed over the material in the first and second recesses; and

a second semiconductor substrate coupled to the first semiconductor substrate such that the first and second substrates are separated by at least a portion of at least the second layer;

wherein the material in the first recess is exposed through the backside surface of the first substrate.

16. The apparatus of claim 15 wherein the first and second semiconductor substrates are coupled via wafer-to-wafer bonding.

17. The apparatus of claim 15 wherein the material in the first recess protrudes from the backside surface by an amount ranging between about 5 nm and about 2000 nm.

18. The apparatus of claim 15 wherein the material is coplanar with the backside surface of the first substrate.

19. The apparatus of claim 15 wherein the first recess is formed in a first region of the first substrate and the second recess in a second region of the first substrate such that the first region, but not the second region, comprises a scribe region.

20. The apparatus of claim 15 wherein the material in the first recess that is exposed through the backside surface of the first substrate acts as an alignment mark and the material in the second recess acts as a shallow trench isolation recess.