SURFACE DEPRESSIONS FOR DIE-TO-DIE INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS

• US 20090321947A1
• Filed: 06/27/2008
• Published: 12/31/2009
• Est. Priority Date: 06/27/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pratt, David S.
• Granted Patent: US 7,800,238 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16147 the bump connector connecting to a bonding area disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/2518 being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/8121 using a reflow oven
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

Stacked microelectronic dies employing die-to-die interconnects and associated systems and methods are disclosed herein. In one embodiment, a stacked system of microelectronic dies includes a first microelectronic die, a second microelectronic die attached to the first die, and a die-to-die interconnect electrically coupling the first die with the second die. The first die includes a back-side surface, a surface depression in the back-side surface, and a first metal contact located within the surface depression. The second die includes a front-side surface and a second metal contact located at the front-side surface and aligned with the first metal contact of the first die. The die-to-die interconnect electrically couples the first metal contact of the first die with the second metal contact of the second die and includes a flowable metal layer that at least partially fills the surface depression of the first die.

Claims

1. A system of stacked microelectronic dies, comprising:

a first microelectronic die having a back-side surface, a surface depression in the back-side surface, and a first metal contact located within the surface depression;

a second microelectronic die having a front-side surface and a second metal contact located at the front-side surface and aligned with the first metal contact; and

a die-to-die interconnect coupling the first metal contact with the second metal contact, the die-to-die interconnect including a flowable metal material that at least partially fills the surface depression.

2. The system of claim 1 wherein the first die further includes a substrate, and wherein the surface depression is lined with a dielectric layer that separates the flowable metal layer of the die-to-die interconnect from the substrate of the first die.

3. The system of claim 1, further comprising a through-die interconnect extending through the first die and being electrically coupled with the flowable metal of the die-to-die interconnect.

4. The system of claim 1 wherein the flowable metal layer of the die-to-die interconnect comprises a reflowed solder bump.

5. The system of claim 1 wherein the back-side surface of the first die is contacting the front-side surface of the second die.

6. The system of claim 1 wherein the back-side surface of the first die is separated from the front-side surface of the second die by a gap having a thickness of less than 0.4 mm.

7. The system of claim 1 wherein the surface depression comprises a first surface depression, the die-to-die interconnect comprises a first die-to-die interconnect, and the flowable metal material comprises a first flowable metal material, and wherein the first die further includes a second surface depression having a second flowable metal material that at least partially fills the second surface depression, the second flowable metal material being associated with a second die-to-die interconnect and being electrically isolated from the first flowable metal material.

8. The system of claim 7 wherein the first metal contact does not project beyond a plane defined by the back-side surface of the first microelectronic die.

9. A microelectronic workpiece, comprising:

a substrate having a front-side surface, a back-side surface, and a recessed surface in the back-side surface;

an alignment feature located at the front-side surface of the substrate, wherein the back-side surface of the substrate has a first topography and the recessed surface has a second topography, the first topography being smoother than the second topography to enhance the optical detection of the alignment feature through the substrate; and

a pass-through interconnect extending through the substrate, wherein at least a portion of the pass-through interconnect is at the recessed surface.

10. The microelectronic workpiece of claim 9 wherein the pass-through interconnect includes a projection portion that projects beyond the recessed surface but not the back-side surface, and wherein the workpiece further comprises a die-to-die interconnect coupled to the projection portion of the pass-through interconnect.

11. The microelectronic workpiece of claim 9, further comprising a layer of reflowed metal coupled to the pass-through interconnect and at least partially surrounding the pass-through interconnect.

12. An interconnect structure for electrically coupling a first microelectronic die with a second microelectronic die, comprising:

a metal interconnect extending through the first die to a back-side of the first die and projecting beyond a recessed surface at the back-side of the die;

a metal contact of the second die aligned with the interconnect; and

a layer of reflowed metal at least partially surrounding the interconnect and electrically coupling the interconnect to the metal contact of the second die, the layer of reflowed metal conforming to a shape defined by the recessed surface, the interconnect, and the metal contact of the second die.

13. The interconnect structure of claim 12, further comprising a dielectric layer positioned between the layer of reflowed metal and the recessed surface of the substrate.

14. The interconnect structure of claim 12, further comprising an under bump metallization layer positioned between the layer of reflowed metal and a portion of the interconnect.

15. The interconnect structure of claim 12 wherein the recessed surface, the interconnect, and the metal contact define a first volume, and wherein the layer of reflowed metal has an associated second volume that is less than or equal to the first volume.

16-25. -25. (canceled)

26. A system of stacked microelectronic dies, comprising:

a first microelectronic die having a back-side surface, a plurality of surface depressions in the back-side surface, and a plurality of through-die interconnects extending through the first microelectronic die, wherein each surface depression has a recessed surface spaced inwardly from a plane defined by the back-side surface, and wherein the through-die interconnects are aligned with corresponding depressions in the back-side surface and have contact portions projecting beyond the recessed surfaces;

a second microelectronic die having a front-side surface and a plurality of metal contacts located at the front-side surface, wherein the metal contacts are aligned with corresponding through-die interconnects; and

a plurality of die-to-die interconnects, wherein each die-to-die interconnect couples a contact portion of one of the through-die interconnects with a corresponding metal contact at the front side of the second microelectronic die, and each die-to-die interconnect comprises a reflowed metal material that at least partially fills one of the surface depressions such that the die-to-die interconnects are electrically isolated from each other.

27. The system of claim 26, further comprising a spun-on dielectric layer on the back-side surface and the recessed surfaces of the first microelectronic die.

28. The system of claim 26 wherein individual surface depressions have a Volume V₁ and individual die-to-die interconnects have a Volume V₂ less than or equal to Volume V₁.

29. The system of claim 26 wherein individual surface depressions have a volume V₁ and individual die-to-die interconnects have a volume V₂ greater than volume V₁.

30. The system of claim 26 wherein individual die-to-die interconnects comprise reflowed metal pumps that conform to the surface depressions in the back-side of the first microelectronic die.

31. The system of claim 26, further comprising a dielectric layer on the back-side surface and the recessed surfaces of the first microelectronic die, and wherein the front-side surface of the second microelectronic die contacts the dielectric layer on the back-side surface of the first microelectronic die, and wherein individual die-to-die interconnects are contained in corresponding surface depressions in the first microelectronic die.