METHOD FOR STACKING DEVICES

• US 20090321948A1
• Filed: 06/27/2008
• Published: 12/31/2009
• Est. Priority Date: 06/27/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chao, Clinton, Chen, Chen-Shien, Wang, Dean, Karta, Tjandra Winata, Lee, Chien-Hsiun, Lii, Mirng-Ji
• Granted Patent: US 8,334,170 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/27416 Spin coating
• CPC Class Codes: H01L 2224/27436 Lamination of a preform, e.g. foil, sheet or layer
• CPC Class Codes: H01L 2224/27848 Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73104 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/75744 in the lower part of the bonding apparatus, e.g. in the apparatus chuck
• CPC Class Codes: H01L 2224/8121 using a reflow oven
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/8321 using a reflow oven
• CPC Class Codes: H01L 2224/83856 Pre-cured adhesive, i.e. B-stage adhesive
• CPC Class Codes: H01L 2224/83862 Heat curing
• CPC Class Codes: H01L 2224/83986 Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2224/9205 Intermediate bonding steps, i.e. partial connection of the semiconductor or solid-state body during the connecting process
• CPC Class Codes: H01L 2224/9211 Parallel connecting processes
• CPC Class Codes: H01L 2224/9221 Parallel connecting processes
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A method for fabricating a semiconductor device is provided which includes providing a first device, a second device, and a third device, providing a first coating material between the first device and the second device, the first coating material being uncured, providing a second coating material between the second device and the third device, the second coating material being uncured, and thereafter, curing the first and second coating materials in a same process.

Claims

1. A method for fabricating a semiconductor device, the method comprising:

providing a first device, a second device, and a third device;

providing a first coating material between the first device and the second device;

providing a second coating material between the second device and the third device; and

thereafter, curing the first and second coating materials in a same process.

2. The method of claim 1,

wherein the first, second, and third devices each include a circuit;

wherein the first and second devices each include a through-silicon via (TSV) structure;

including, responsive to the curing, electrically coupling the circuits of the first, second, and third devices using the TSV structure of the first and second devices; and

wherein the first and second coating materials both include a flux component that facilitates the coupling.

3. The method of claim 1, wherein the first, second, and third devices are each one of a die and a wafer.

4. The method of claim 3, including:

providing a fourth device, the fourth device being one of a die and a wafer;

providing a third coating material between the third device and the fourth device; and

wherein the curing includes curing the third coating material in the same process as the first and second coating materials.

5. The method of claim 1, including pre-treating the first and second coating materials prior to the curing.

6. The method of claim 5, wherein the pre-treating includes heating the first and second coating materials to a temperature that is less than a curing temperature of the first and second coating materials.

7. The method of claim 1, including post-treating the first and second coating materials after the curing.

8. The method of claim 1, wherein the providing the first coating material includes forming the first coating material on the first device, and overlying the second device on the first coating material and the first device;

and

wherein the providing the second coating material includes forming the second coating material on the second device, and overlying the third device on the second coating material and the second device.

9. The method of claim 1, wherein the providing the first coating material includes forming the first coating material on the second device, and overlying the second device with the first coating material on the first device;

and

wherein the providing the second coating material includes forming the second coating material on the third device, and overlying the third device with the second coating material on the second device.

10. A semiconductor device, comprising:

a first device;

a second device overlying the first device and electrically coupled to the first device;

a third device overlying the second device and electrically coupled to the second device;

a first coating material disposed between the first and second devices; and

a second coating material disposed between the second and third devices;

wherein the first and second coating materials are configured with substantially similar thermal histories.

11. The semiconductor device of claim 10, wherein the first and second coating materials are configured with substantially the same curing cycles.

12. The semiconductor device of claim 11, wherein the first, second, and third devices are each one of a die and a wafer.

13. The semiconductor device of claim 12, further comprising a fourth device overlying the third device and electrically coupled to third device, the fourth device being one of a die and a wafer;

and

a third coating material disposed between the third and fourth devices, the third coating material having a substantially same curing cycle as the curing cycles of the first and second coating materials.

14. The semiconductor device of claim 10, wherein the first, second, and third devices each include a plurality of through silicon via (TSV) structures.

15. The semiconductor device of claim 14, wherein one of the TSV structures of the first device is electrically coupled to one of the TSV structures of the second device;

and

wherein one of the TSV structures of the second device is electrically coupled to one of the TSV structures of the third device.

16. The semiconductor device of claim 10, wherein the first device includes a plurality of conductive bumps for connecting to another semiconductor device.

17. The semiconductor device of claim 10, further comprising a carrier substrate for supporting a structure;

and

wherein the first device overlies the carrier substrate and is secured to the carrier substrate.

18. A method for fabricating a stacked semiconductor device, the method comprising:

providing a first device having a circuit and a first coating material formed thereon;

stacking a second device on the first coating material and the first device, the second device having a circuit and a second coating material formed thereon;

stacking a third device on second coating material and the second device, the third device having a circuit; and

thereafter, performing one thermal process that electrically couples the circuits of the first, second, and third devices to form a circuit of the stacked semiconductor device, and that cures the first and second coating materials.

19. The method of claim 18, including pre-treating the first and second coating materials prior to the one thermal process, wherein a temperature of the pre-treating is from about 80°

C. to about 150°

C.

20. The method of claim 18, including post-treating the first and second coating materials after the one thermal process, wherein a temperature of the post-treating is from about 100°

C. to about 200°

C.

21. The method of claim 18, wherein a temperature of the one thermal process is from about 200°

C. to about 300°

C.

22. The method of claim 18, including selecting the first and second coating materials to be one of a B-stage polymer and a solid film.