CIRCUIT SUBSTRATE HAVING CIRCUIT WIRE FORMED OF CONDUCTIVE POLARIZATION PARTICLES, METHOD OF MANUFACTURING THE CIRCUIT SUBSTRATE AND SEMICONDUCTOR PACKAGE HAVING THE CIRCUIT WIRE

• US 20090321953A1
• Filed: 09/09/2008
• Published: 12/31/2009
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KANG, Tae Min
• Granted Patent: US 7,786,600 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/02315 Self-assembly processes
• CPC Class Codes: H01L 2224/02317 by local deposition
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/24998 Reinforcing structures, e.g. ramp-like support
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/82007 : involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting a build-up interconnect during or after the bonding process
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5328 : containing conductive organic materials or pastes, e.g. conductive adhesives, inks
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/0293 : Individual printed conductors which are adapted for modification, e.g. fusable or breakable conductors, printed switches
• CPC Class Codes: H05K 1/095 : for polymer thick films, i.e. having a permanent organic polymeric binder
• CPC Class Codes: H05K 2203/0126 : Dispenser, e.g. for solder paste, for supplying conductive paste for screen printing or for filling holes
• CPC Class Codes: H05K 2203/105 : Using an electrical field; Special methods of applying an electric potential electroplating H05K2203/0723
• CPC Class Codes: H05K 2203/173 : Adding connections between adjacent pads or conductors, e.g. for modifying or repairing programmable, customizable or modifiable circuits H05K1/0286
• CPC Class Codes: H05K 3/105 : by conversion of non-conductive material on or in the support into conductive material, e.g. by using an energy beam
• CPC Class Codes: H05K 3/1241 : by ink-jet printing or drawing by dispensing
• CPC Class Codes: H05K 3/4053 : by thick-film techniques
• CPC Class Codes: H05K 3/4685 : Manufacturing of cross-over conductors
• CPC Class Codes: Y10T 29/49162 : by using wire as conductive path

Abstract

A circuit substrate includes a substrate body having a first terminal and a second terminal separated from the first terminal. A circuit wire includes a wiring unit for electrically connecting the first and second terminals by electrically connecting conductive polarization particles that include a first polarity and a second polarity that is opposite to the first polarity. The circuit wire also includes an insulation unit for insulating the wiring unit.

Claims

1. A circuit substrate, comprising:

a substrate body;

a first terminal disposed over the substrate body;

a second terminal disposed over the substrate body and separated from the first terminal; and

a circuit wire comprising;

a wiring unit for electrically connecting the first and second terminals by electrically connecting a plurality of conductive polarization particles, wherein each conductive polarization particle of the plurality of conductive polarization particles has a first polarity and a second polarity that is opposite to the first polarity; and

an insulation unit for insulating the wiring unit.

2. The circuit substrate according to claim 1, wherein the plurality of conductive polarization particles are comprised of a conductive rheological material.

3. The circuit substrate according to claim 1, further comprising:

a third terminal disposed over the substrate body;

a fourth terminal disposed over the substrate body and separated from the third terminal; and

an intersection wire comprising an intersection wiring unit and an intersection insulation unit for insulating the intersection wiring unit, the intersection wiring unit comprising;

a plurality of conductive polarization particles for electrically connecting the third and fourth terminals,

wherein the intersection wire intersects the circuit wire over the substrate body.

4. The circuit substrate according to claim 1, further comprising:

a third terminal disposed over the substrate body;

a metal wire disposed over the substrate body;

an additional circuit wire comprising an additional wiring unit and an additional insulation unit for insulating the additional wiring unit, the additional wiring unit comprising;

a plurality of conductive polarization particles for electrically connecting the metal wire and the third terminal.

5. The circuit substrate according to claim 1, further comprising:

a first connection unit extending from the first terminal along the substrate body; and

a second connection unit extending from the second terminal along the substrate body,

wherein a first end of the wiring unit is connected to the first connection unit and a second end of the wiring unit, opposite the first end, is connected to the second connection unit.

6. A method of manufacturing a circuit substrate, comprising the steps of:

forming a first terminal on a surface of a substrate body;

forming a second terminal on the surface of the substrate body;

forming a preliminary circuit wire by connecting the first and second terminals with a wiring material, the wiring material comprising;

a plurality of conductive polarization particles having a first polarity and a second polarity that is opposite the first polarity; and

a flowable insulator;

forming a wiring unit electrically connected to the first and second terminals by applying a first power having the first polarity to the first terminal and a second power having the second polarity to the second terminal and thus electrically connecting the conductive polarization particles within the flowable insulator; and

forming an insulation unit for securing and insulating the wiring unit by curing the flowable insulator.

7. The method according to claim 6, wherein the conductive polarization particles are formed of conductive rheological material.

8. The method according to claim 6, wherein the step of forming the preliminary circuit wire is carried out by one of a printing process, a dispensing process;

and a silk screen printing process.

9. The method according to claim 6, wherein the step of forming the substrate body comprises the step of:

forming a first connection unit extending from the first terminal along the substrate body and a second connection unit extending from the second terminal along the substrate body,

wherein a first end of the wiring unit is connected to the first connection unit and a second end that is opposite the first end is connected to the second connection unit.

10. A semiconductor package, comprising:

a semiconductor chip;

a plurality of bonding pads formed over an upper surface of the semiconductor chip;

a plurality of conductive land patterns separated from the plurality of bonding pads; and

a plurality of circuit wires, each circuit wire comprising;

a wiring unit for electrically connecting a bonding pad of the plurality of bonding pads and a conductive land pattern of the plurality of land patterns corresponding to the bonding pad by electrically connecting a plurality of conductive polarization particles respectively having a first polarity and a second polarity that is opposite to the first polarity; and

an insulation unit for insulating the wiring unit.

11. The semiconductor package according to claim 10, wherein the plurality of conductive polarization particles are comprised of a conductive rheological material.

12. The semiconductor package according to claim 10, wherein the plurality of land patterns are comprised of an anisotropic conductive film.

13. The semiconductor package according to claim 10, wherein the plurality of land patterns are comprised of a metal plate.

14. The semiconductor package according to claim 10, wherein the plurality of land patterns comprise a connection unit extending along the upper surface of the semiconductor chip, and an end of the circuit wire is electrically connected to the connection unit.

15. The semiconductor package according to claim 10, wherein at least two circuit wires of the plurality of circuit wires intersect each other.

16. The semiconductor package according to claim 10, further comprising:

a solder resist pattern disposed over the upper surface of the semiconductor chip and having openings for exposing both the plurality of land patterns and connection members respectively connected to the plurality of land patterns through the openings.

17. The semiconductor package according to claim 16, wherein the connection member comprise a conductive ball.

18. The semiconductor package according to claim 10, wherein the land patterns are disposed over a surface of the semiconductor chip.

19. The semiconductor package according to claim 10, further comprising:

a molding member for covering a lower surface of the semiconductor chip, that is opposite to the upper surface of the semiconductor chip, and side surfaces of the semiconductor chip connected with the upper surface of the semiconductor chip.

20. The semiconductor package according to claim 19, wherein one or more of the land patterns of the plurality of land patterns are disposed over the semiconductor chip and the remaining land patterns of the plurality of land patterns are disposed over the molding member.

21. The semiconductor package according to claim 10, further comprising:

a substrate;

a plurality of connection pads disposed on the substrate at positions corresponding to the plurality of land patterns; and

bumps for electrically connecting the plurality of connection pads and the plurality of land patterns.

22. The semiconductor package according to claim 21, further comprising:

a gap filling member filled in a gap formed between the semiconductor chip and the substrate.

23. A semiconductor package, comprising:

a substrate having connection pads formed thereon;

a semiconductor chip module comprising a plurality of semiconductor chips having pads formed thereon; and

a plurality of circuit wires, each circuit wire comprising;

a wiring unit for electrically connecting a pad of respective semiconductor chips and a connection pad corresponding to the pad by electrically connecting a plurality of conductive polarization particles having a first polarity and a second polarity opposite to the first polarity; and

an insulation unit for covering the wiring unit.

24. The semiconductor package according to claim 23, wherein the semiconductor chips are stacked in a stepped shape to expose the pads of the respective semiconductor chips.

25. The semiconductor package according to claim 23, wherein the plurality of conductive polarization particles are comprised of a conductive rheological material.

26. The semiconductor package according to claim 23, further comprising:

a guide member disposed at a side surface of respective semiconductor chips forming an inclined plane having an obtuse angle with respect to an upper surface of the respective semiconductor chip.

27. A semiconductor package, comprising:

a substrate having connection pads formed thereon;

a semiconductor chip module comprising a plurality of semiconductor chips respectively having exposed chip selection pads; and

a plurality of circuit wires, each circuit wire comprising;

a wiring unit for electrically connecting a chip selection pad of respective semiconductor chips and a connection pad corresponding to the chip selection pad by electrically connecting a plurality of conductive polarization particles having a first polarity and a second polarity opposite the first polarity; and

an insulation unit for covering the wiring unit.

28. The semiconductor package according to claim 27, wherein the plurality of semiconductor chips are stacked in a stepped shape to expose the chip selection pads formed in the respective semiconductor chips.

29. The semiconductor package according to claim 27, wherein the plurality of conductive polarization particles are comprised of a conductive rheological material.

30. The semiconductor package according to claim 27, further comprising:

a guide member disposed at a side surface of respective semiconductor chips forming an inclined plane having an obtuse angle with respect to an upper surface of the respective semiconductor chip.

31. The semiconductor package according to claim 27, wherein the semiconductor chip further comprises:

a data pad;

a data redistributions electrically connected to the data pad; and

a data through electrode passing through the semiconductor chip and electrically connected to the data redistribution.

32. The semiconductor package according to claim 27, wherein the chip selection pads of the semiconductor chips are electrically connected to one connection pad by circuit wires that intersect each other.

33. A semiconductor package, comprising:

a semiconductor chip comprising;

a circuit unit;

a bonding pad electrically connected to the circuit unit; and

a through hole electrically connected to the circuit unit;

a through electrode unit disposed within the through hole and electrically connected to the bonding pad, the through unit comprising a plurality of conductive polarization particles having a first polarity and a second polarity opposite the first polarity and electrically connected to each other; and

insulation units for insulating the through electrodes.

34. The semiconductor package according to claim 33, wherein the plurality of conductive polarization particles are comprised of a conductive rheological material.

35. The semiconductor package according to claim 33, wherein the bonding pad is disposed at a position corresponding to the through hole.

36. The semiconductor package according to claim 35, wherein the bonding pad is disposed over an edge of the upper surface of the semiconductor chip.

37. The semiconductor package according to claim 35, further comprising:

a conductive connection member for partially covering or completely covering at least one end of the through electrode unit.

38. The semiconductor package according to claim 37, wherein the conductive connection member comprises an anisotropic conductive film having resin and conductive particles arranged within the resin.

39. The semiconductor package according to claim 37, wherein the conductive connection member comprises a conductive layer.

40. The semiconductor package according to claim 39, wherein the conductive layer comprises a solder.

41. The semiconductor package according to claim 33, wherein the through hole and a bonding pad corresponding to the through hole are separated from each other by a given distance.

42. The semiconductor package according to claim 33, further comprising:

a wiring unit for electrically connecting the through electrode unit and a bonding pad corresponding to the through electrode unit.

43. The semiconductor package according to claim 33, wherein two or more semiconductor chips are stacked.