SERIES AND PARALLEL HYBRID SWITCHED CAPACITOR NETWORKS FOR IC POWER DELIVERY

• US 20090322304A1
• Filed: 06/30/2008
• Published: 12/31/2009
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kamgaing, Telesphor, Oraw, Bradley S.
• Granted Patent: US 8,330,436 B2
• Time in Patent Office: Days
• US Class Current: 323/312
• CPC Class Codes: H02J 1/102 being switching converters H02J1/108, H02J1/12 take precedence
• CPC Class Codes: H02J 9/005 using a power saving mode for copiers G03G15/5004
• CPC Class Codes: H02M 1/008 Plural converter units for generating at two or more independent and non-parallel outputs, e.g. systems with plural point of load switching regulators
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

Series switches for power delivery. A regulator operated as a current source is arranged in parallel with a switched capacitor divider. A switched capacitor divider is configured in series with a plurality of linear regulators with each regulating one of a plurality of voltage outputs from the switched capacitor divider. In another embodiment, a series switch bridge has a first pair of switches connected in series with a second pair of switches across a voltage input, each switch within a pair of switches is switched in-phase with the other while the first pair of switches is switched out of phase with the second pair of switches. A balancing capacitor is coupled across one switch in both the first and second pair to be in parallel when either of the pair of switches is closed to reduce a charge imbalance between the switches.

Claims

1. A power delivery network for an integrated circuit, the network comprising:

a hybrid parallel power conversion stage including converter of a first type configured in parallel with a converter of a second type, each converter coupled with an input voltage to provide a regulated output current to power the integrated circuit.

2. The power delivery network of claim 1, wherein the converter of the first type is a switched capacitor converter and the converter of the second type is configured as a current source.

3. The power delivery network of claim 1, wherein the switched capacitor converter is a switched capacitor divider and wherein the converter of the second type is a buck regulator configured to operate in a current mode.

4. The power delivery network of claim 1, wherein the switched capacitor converter is a switched capacitor divider and wherein the converter of the second type is a linear regulator configured to operate as a current source.

5. The power delivery network of claim 3, wherein the integrated circuit is a microprocessor, the switched capacitor divider includes a plurality of low voltage logic MOSFETs configured in series across the input voltage.

6. The power delivery network of claim 1, further comprising a current controller coupled with the converter of the second type to set the portion of the regulated output current provided by the converter of the second type.

7. The power delivery network of claim 1, further comprising a voltage regulator stage configured in series with the hybrid parallel power conversion stage, wherein the voltage regulator stage output is coupled with an input to the hybrid parallel power conversion stage or the voltage regulator stage input is coupled with an output of the hybrid parallel power conversion stage.

8. The power delivery network of claim 7, wherein the voltage regulator stage further comprises at least one of a buck regulator or a linear regulator.

9. The power deliver network of claim 4, wherein the switched capacitor divider further comprises:

a plurality of FETs configured with drain terminals coupled with source terminals to be in series across a voltage input; and

a plurality of capacitors connected across the voltage input and coupled with the series switches to divide the input voltage into a plurality of first voltage outputs; and

a plurality of linear regulators, each linear regulator coupled with one of the plurality of first voltage outputs to regulate a second voltage output.

10. The power deliver network of claim 9, wherein alternating ones of the plurality of FETs have gate terminals coupled together to form a first and second pair of gate coupled FETs, and wherein the first pair of gate coupled FETs is configured to switch between a low state and a high state within a switching cycle while the second pair of gate coupled FETs is configured to switch to a state opposite the first pair of gate coupled FETs;

and wherein the plurality of capacitors further comprise;

a first capacitor coupled to a drain terminal of each of the first pair of gate coupled FETs; and

a second capacitor coupled to a drain terminal of each of the second pair of gate coupled FETs.

11. A power delivery network to deliver power one or more integrated circuits at a plurality of voltages, the network comprising:

a switched capacitor divider (SCD) comprising;

a plurality of FETs configured with drain terminals coupled with source terminals to be in series across a voltage input; and

a plurality of capacitors connected across the voltage input and coupled with the series switches to divide the input voltage into a plurality of first voltage outputs; and

a plurality of linear regulators, each linear regulator coupled with one of the plurality of first voltage outputs to regulate a second voltage output.

12. The power delivery network of claim 11, wherein alternating ones of the plurality of FETs have gate terminals coupled together to form a first and second pair of gate coupled FETs, and wherein the first pair of gate coupled FETs is configured to switch between a low state and a high state within a switching cycle while the second pair of gate coupled FETs is configured to switch to a state opposite the first pair of gate coupled FETs;

and wherein the plurality of capacitors further comprise;

a first capacitor coupled to a drain terminal of each of the first pair of gate coupled FETs; and

a second capacitor coupled to a drain terminal of each of the second pair of gate coupled FETs, both of the first and second capacitors to be alternately charged and discharged within the switching cycle when the first and second pairs of gate coupled FETs are switched between low and high states.

13. The power delivery network of claim 11, further comprising a buck regulator stage to provide the input voltage to the SCD.

14. The power delivery network of claim 11, wherein each of the plurality of linear regulators is coupled to an output circuit including one of the plurality of ICs.

15. A power delivery network to power an integrated circuit, comprising:

a voltage input; and

a series switch bridge, wherein the series switch bridge further comprises;

a first pair of switches connected in series with a second pair of switches across the voltage input, wherein each pair of switches includes a first switch having a drain terminal coupled with a source terminal of a second switch with gate terminals coupled together, and wherein the first pair of switches is configured to switch between a low state and a high state within a switching cycle while the second pair of switches is configured to switch to a state opposite the first pair;

a balancing capacitor coupled with a node between the switches of the first pair and coupled with a node between the switches of the second pair; and

a voltage output coupled with a node between the first pair of switches and the second pair of switches, the voltage output to be coupled with the IC to be powered.

16. The power delivery network of claim 15, wherein the voltage input is at least 3V and the switches are low voltage logic FETs configured to operated at approximately 1.5V.

17. The power delivery network of claim 15, wherein the balancing capacitor has a capacitance value at least an order of magnitude larger than a parasitic output capacitance of any switch of the first and second switch pairs.

18. The power delivery network of claim 15, wherein the series switch bridge is integrated with low voltage CMOS FETs onto the package of the integrated circuit.

19. The power delivery network of claim 15, wherein the first pair and second pair of switches comprises a bridge circuit providing an output voltage equal to approximately half the voltage input.

20. The power delivery network of claim 15, wherein the series switch bridge is a component of voltage regulator.