Passive Mixer Power Detector Method and Apparatus

• US 20090322312A1
• Filed: 06/26/2008
• Published: 12/31/2009
• Est. Priority Date: 06/26/2008
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Arnborg, Torkel
• Granted Patent: US 7,786,720 B2
• Time in Patent Office: Days
• US Class Current: 324/120
• CPC Class Codes: G01R 21/01 in circuits having distributed constants G01R21/04, G01R21/07, G01R21/09, G01R21/12 take precedence
• CPC Class Codes: H03D 1/2272 using FET's H03D1/2209, H03D1/2245 and H03D1/2281 take precedence
• CPC Class Codes: H04B 17/10 of transmitters

Abstract

The power level of an RF signal is detected using a circuit having relatively low DC offset, high dynamic range, small frequency and temperature dependence and low flicker noise. According to one embodiment, the power detector circuit comprises a chain of amplifiers and a passive mixer. The chain of amplifiers converts the RF input signal to a supply-limited RF square wave signal. The passive mixer passively mixes the supply-limited RF square wave signal with the RF input signal and in response generates a rectified output signal that tracks the amplitude of the RF input signal.

Claims

1. A method of generating a rectified signal for power detection, comprising:

generating a supply-limited radio frequency (RF) square wave signal from an RF input signal; and

passively mixing the supply-limited RF square wave signal with the RF input signal to generate a rectified output signal that tracks the amplitude of the RF input signal.

2. The method of claim 1, wherein generating a supply-limited RF square wave signal from an RF input signal comprises:

applying the RF input signal to a chain of amplifiers; and

operating at least one of the amplifiers at the end of the chain in saturation for each non-negligible amplitude level of the RF input signal.

3. The method of claim 2, wherein operating at least one of the amplifiers at the end of the chain in saturation for each non-negligible amplitude level of the RF input signal comprises:

inputting a differential signal to a pair of CMOS inverters coupled between a power supply and a bias device in a differential amplifier configuration; and

outputting a differential signal from the pair of CMOS inverters that is saturated at the supply voltage while the differential signal has non-negligible amplitude.

4. The method of claim 2, comprising preventing the rectified output signal from having negligible amplitude when the RF input signal has non-negligible amplitude.

5. The method of claim 4, wherein preventing the rectified output signal from having negligible amplitude when the RF input signal has non-negligible amplitude comprises coupling a sufficient number of inverting amplifiers together in the chain to prevent a 90°

phase difference between the RF input signal and the supply-limited RF square wave signal.

6. The method of claim 5, wherein coupling a sufficient number of inverting amplifiers together in the chain to prevent a 90°

phase difference between the RF input signal and the supply-limited RF square wave signal comprises coupling a sufficient number of the inverting amplifiers together in the chain such that the total phase shift caused by the chain of amplifiers is centered around n*180° and

also avoids the 90°

phase difference, where n is an integer.

7. The method of claim 1, wherein passively mixing the supply-limited RF square wave signal with the RF input signal to generate the rectified output signal comprises:

switchably coupling the RF input signal to a load in a first configuration when the supply-limited RF square wave signal is of a first polarity; and

reversing the configuration when the supply-limited RF square wave signal changes polarity.

8. The method of claim 1, comprising filtering the rectified output signal to yield a DC output voltage that tracks the amplitude of the RF input signal.

9. A power detector, comprising:

a chain of amplifiers configured to convert a radio frequency (RF) input signal to a supply-limited RF square wave signal; and

a passive mixer configured to passively mix the supply-limited RF square wave signal with the RF input signal and in response, generate a rectified output signal that tracks the amplitude of the RF input signal.

10. The power detector of claim 9, wherein at least one of the amplifiers at the end of the chain is configured to operate in saturation for each non-negligible amplitude level of the RF input signal.

11. The power detector of claim 10, wherein the at least one amplifier at the end of the chain comprises a pair of CMOS inverters coupled between a power supply and a bias device in a differential amplifier configuration, the pair of CMOS inverters configured to output a differential signal saturated at the supply voltage while a differential signal input to the pair of CMOS inverters has non-negligible amplitude.

12. The power detector of claim 9, wherein the chain of amplifiers comprises a sufficient number of inverting amplifiers to prevent a 90°

phase difference between the RF input signal and the supply-limited RF square wave signal.

13. The power detector of claim 12, wherein the chain of amplifiers comprises a sufficient number of the inverting amplifiers such that the total phase shift caused by the chain of amplifiers is centered around n*180°

and also avoids the 90°

phase difference, where n is an integer.

14. The power detector of claim 9, wherein a minimum number of amplifiers included in the chain satisfies:

$m=\frac{\log <br><br><br><br>E-\log <br><br><br><br>V_o}{\log <br><br><br><br>A_0-\log <br><br>\sqrt{1+{\left(\frac{f}{f_0}\right)}^2}},$

where m represents the minimum number of amplifiers, E represents supply voltage, V_o represents the amplitude of the RF input signal, A₀ represents a DC gain factor for each amplifier, f₀ represents an upper frequency limit of each amplifier and f represents the frequency of the RF input signal.

15. The power detector of claim 9, wherein at least some of the amplifiers included in the chain are capacitively-coupled.

16. The power detector of claim 9, wherein the passive mixer is configured to switchably couple the RF input signal to a load in a first configuration when the supply-limited RF square wave signal is of a first polarity and reverse the configuration when the supply-limited RF square wave signal changes polarity.

17. The power detector of claim 16, wherein the passive mixer comprises:

a first branch configured to couple a first signal input of the differential RF input signal to a first node of the load when a first signal component of the differential supply-limited RF square wave signal is positive;

a second branch configured to couple a second signal input of the differential RF input signal to a second node of the load when the first signal component of the differential supply-limited RF square wave signal is positive;

a third branch configured to couple the first signal input of the differential RF input signal to the second node of the load when the second signal component of the differential supply-limited RF square wave signal is positive; and

a fourth branch configured to couple the second signal input of the differential RF input signal to the first node of the load when the second signal component of the differential supply-limited RF square wave signal is positive.

18. The power detector of claim 9, further comprising a filter configured to convert the rectified output signal to a DC output voltage.