Integrated Tester Chip Using Die Packaging Technologies

• US 20090322368A1
• Filed: 08/15/2008
• Published: 12/31/2009
• Est. Priority Date: 06/27/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Jha, Sanjay K., Kaskoun, Kenneth
• Granted Patent: US 8,717,057 B2
• Time in Patent Office: Days
• US Class Current: 324/750.16
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls
• CPC Class Codes: G01R 31/3187 Built-in tests
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

By constructing a universal test circuit on a tester chip, and stacking the tester chip in an IC package together with operational circuit chips to be tested, the problems inherent with external IC testing are reduced. The tester chip can be standardized across a number of different chip combinations and, if desired, pre-programmed during manufacturing for a particular package. The tester chip interfaces to other chips in the stack advantageously are standardized.

Claims

1. A tester chip containing a test circuit operable for testing any one of a number of different operational circuits, wherein said different operational circuits are mounted in a same IC package with said test circuit.

2. The tester chip of claim 1 wherein said tester chip can be removed from said package without interfering with normal operation of said mounted operational circuits within said package.

3. The tester chip of claim 1 wherein said IC package has a plurality of tiers of IC devices and said tester chip is mounted on one of said tiers.

4. The tester chip of claim 1 further comprising:

a computer readable medium storing a program designed to control said test circuit on said tester chip such that said test circuit performs validation testing on said operational circuits.

5. The tester chip of claim 4 wherein said program is contained in a memory separate from said tester chip.

6. The tester chip of claim 5 wherein said memory is mounted on one of a plurality of tiers of IC devices within the IC package.

7. The tester chip of claim 6 wherein said program is downloaded to said memory after said memory is positioned in said IC package.

8. A method for testing a stacked IC device within an IC package, said method comprising:

positioning a plurality of chips on a plurality of tiers of said stacked IC package, said positioning comprising electrically coupling said plurality of chips such that said coupled chips function as a device; and

testing a function of said device under control of at least one of said interconnected chips.

9. The method of claim 8 further comprising:

providing test instructions to at least one of the chips.

10. The method of claim 9 wherein said test instructions are provided to at least one of said chips prior to said positioning.

11. An IC package comprising:

at least one operational circuit constructed on a first chip; and

a test circuit constructed on a second chip that is coupled to the first chip, said test circuit capable of testing said operational circuit, as well as a plurality of different types of operational circuits.

12. The package of claim 11 wherein said at least one operational circuit is constructed on different chips, said different chips stacked together within said IC package.

13. The package of claim 11 further comprising:

means for receiving operational instructions unique to said at least one operational circuit, said operational instructions being used to configure said test circuit.

14. The package of claim 13 wherein said operational instructions are contained in a memory resident within said IC package.

15. The package of claim 13 wherein said receiving means comprises:

wireless reception.

16. A method for constructing a stacked IC device, said method comprising:

selecting a plurality of different chips;

selecting at least one tester chip capable of testing a plurality of different combinations of coupled chips; and

stacking said chips, including said tester chip, such that portions of said chips become electrically coupled, wherein said stacked chips form said stacked IC device.

17. The method of claim 16 further comprising:

programming said tester chip to perform testing on said stacked chips.

18. The method of claim 17 further comprising:

removing at least a portion of said tester chip after said testing is performed.

19. The method of claim 17 wherein said programming is performed prior to said stacking.

20. The method of claim 17 wherein said programming is performed from time to time.

21. The method of claim 20 wherein said time to time programming is wirelessly communicated to said stacked IC device.