Power reduction apparatus and method

• US 20090322409A1
• Filed: 06/26/2008
• Published: 12/31/2009
• Est. Priority Date: 06/26/2008
• Status: Abandoned Application

• Current Assignee: Efraim Rotem, Maxim Levit
• Original Assignee: Efraim Rotem, Maxim Levit
• Inventors: Levit, Maxim, Rotem, Efraim
• Application Number:
  US12/215,289
• Publication Number:
  US 20090322409A1
• Time in Patent Office: Days
• US Class Current: 327/513
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Provided is an approach to saving active power through lowering a supply voltage when operating temperature goes up, while substantially maintaining operating performance.

Claims

1. A chip, comprising:

a functional circuit having transistors to implement logic, the transistors to be operated in a temperature range where their strength increases with an increase in temperature; and

a control unit to decrease a voltage supply to the functional circuit when temperature goes up during functional circuit active operation.

2. The chip of claim 1, in which the functional circuit is a processor core.

3. The chip of claim 1, in which the supplied voltage supply is less than 1.0 V.

4. The chip of claim 1, in which the control unit controls the voltage supply in accordance with a data set of Vcc/T correlations.

5. The chip of claim 4, in which the Vcc/T correlations comprise at least one discrete threshold.

6. The chip of claim 4, in which the data set of Vcc/T correlations are based on manufacturing process test results.

7. The chip of claim 4, in which the data set of Vcc/T correlations are programmed into memory accessible to the control unit.

8. The chip of claim 1, in which the supply voltage is controlled in accordance with an acceptable range of voltage versus temperature operating points.

9. The chip of claim 8, in which equilibrium Vcc/T operating points are programmed into a memory to be accessed by the control unit.

10. A method, comprising:

monitoring temperature and performance level for a functional circuit; and

reducing a supply voltage to the functional circuit in an active operating mode in response to the temperature increasing while at least maintaining the desired performance level.

11. The method of claim 10, in which the voltage is reduced in response to the temperature increasing by a sufficient increment.

12. The method of claim 11, in which the functional circuit comprises one or more cores in a processor.

13. The method of claim 12, in which the supply voltage is controlled in accordance with a Vcc/T curve.

14. The method of claim 12, in which the desired performance state is defined by a P state from an operating system.

15. The method of claim 10, in which the supply voltage is controlled to be less than 1 V.

16. A system, comprising:

a chip having a processing core with at least one temperature sensor to monitor an operating temperature; and

a voltage regulator to provide a voltage supply to the core, wherein the chip has a control unit to control the voltage regulator to reduce the voltage supplied to the core in response to the monitored temperature sufficiently increasing.

17. The system of claim 16, in which the chip comprises multiple cores controlled by the control unit to lower their active supply levels when their temperatures sufficiently increase.

18. The system of claim 16, comprising an antenna coupled to the chip to communicatively link it with a wireless network.

19. The system of claim 16, in which the core is formed from transistors made using a 45 nM or smaller process.

20. The system of claim 16, in which the control unit controls the voltage supply in accordance with a data set of Vcc/T correlations.