SYSTEMS AND METHODS FOR ADJUSTING THRESHOLD VOLTAGE

• US 20090322412A1
• Filed: 08/25/2009
• Published: 12/31/2009
• Est. Priority Date: 02/02/2004
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Burr, James B., Masleid, Robert Paul
• Granted Patent: US 8,222,914 B2
• Time in Patent Office: Days
• US Class Current: 327/535
• CPC Class Codes: G01R 31/2621 for testing field effect transistors, i.e. FET's
• CPC Class Codes: H03K 19/0027 in field effect transistor circuits
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

Systems and methods for adjusting threshold voltage. A threshold voltage of a transistor of an integrated circuit is measured. A bias voltage, which when applied to a body well of the transistor corrects a difference between the threshold voltage and a desired threshold voltage for the transistor, is determined. The bias voltage is encoded into non-volatile storage on the integrated circuit. The non-volatile storage can be digital and/or analog.

Claims

1. A method of encoding threshold voltage adjustments for an integrated circuit, said method comprising:

measuring a threshold voltage of a transistor of said integrated circuit;

determining a bias voltage which when applied to a body well of said transistor corrects a difference between said threshold voltage and a desired threshold voltage for said transistor; and

encoding said bias voltage into non-volatile storage on said integrated circuit.

2. The method of claim 1 wherein said transistor is a p channel field effect transistor.

3. The method of claim 1 wherein said transistor is an n channel field effect transistor.

4. The method of claim 1 wherein said non-volatile storage comprises a fuse.

5. The method of claim 1 wherein said non-volatile storage comprises electrically erasable programmable read only memory.

6. The method of claim 1 wherein said encoding stores a digital representation of said bias voltage.

7. The method of claim 6 wherein said digital representation of said bias voltage is accessible by a bias voltage source.

8. The method of claim 6 wherein said digital representation of said bias voltage is accessible by a microprocessor.

9. The method of claim 1 wherein said encoding stores an analog representation of said bias voltage.

10. The method of claim 9 wherein said analog representation of said bias voltage is accessible by a bias voltage source.

11. The method of claim 1 wherein said desired threshold voltage is a nominal process threshold voltage for said integrated circuit.

12. The method of claim 1 wherein said desired threshold voltage is determined based on power consumption characteristics of said integrated circuit at a specific operating frequency.

13. A method of biasing an integrated circuit comprising:

accessing a bias voltage representation from non-volatile storage of said integrated circuit;

generating a bias voltage corresponding to said bias voltage representation; and

applying said bias voltage to a body biasing well of said integrated circuit.

14. The method of claim 13 wherein said generating is performed on said integrated circuit.

15. The method of claim 13 wherein said accessing is performed substantially by hardware.

16. The method of claim 13 wherein said accessing is performed under software control.

17. The method of claim 13 wherein said bias voltage representation is analog.

18. The method of claim 13 wherein said bias voltage representation is digital.

19. The method of claim 13 wherein said applying comprises coupling said bias voltage from a source external to said integrated circuit.

20. A method to correct threshold voltage of an integrated circuit field effect transistor comprising applying a body bias voltage to said field effect transistor to achieve a desired threshold voltage.