INTEGRATION OF SWITCHED CAPACITOR NETWORKS FOR POWER DELIVERY

• US 20090322414A1
• Filed: 06/30/2008
• Published: 12/31/2009
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kamgaing, Telesphor, Oraw, Bradley S.
• Granted Patent: US 8,582,333 B2
• Time in Patent Office: Days
• US Class Current: 327/537
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H02M 1/007 Plural converter units in cascade push-pull DC/DC converters with pre-regulator H02M3/3374; DC-AC converters following a DC-DC stage including a high frequency transformer H02M7/4807; DC-AC converters following a DC-DC conversion stage generating periodically varying voltages H02M7/4826
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators

Abstract

Switched capacitor networks for power delivery to packaged integrated circuits. In certain embodiments, the switched capacitor network is employed in place of at least one stage of a cascaded buck converter for power delivery. In accordance with particular embodiments of the present invention, a two-stage power delivery network comprising both switched capacitor stage and a buck regulator stage deliver power to a microprocessor or other packaged integrated circuit (IC). In further embodiments, a switched capacitor stage is implemented with a series switch module comprising low voltage MOS transistors that is then integrated onto a package of at least one IC to be powered. In certain embodiments, a switched capacitor stage is implemented with capacitors formed on a motherboard, embedded into an IC package or integrated into a series switch module.

Claims

1. A multi-stage power delivery network to deliver power to an integrated circuit (IC), the network comprising:

a switched capacitor divider (SCD) stage comprising;

a series switch module including a plurality of FETs configured in series with drain terminals coupled with source terminals, the series switch module being connected across an input voltage and having a plurality of pinouts coupled with the plurality of FET drain terminals; and

a plurality of capacitors, external to the series switch module, connected across the voltage input and coupled with the plurality of drain pinouts, ones of the plurality of capacitors to be switched by the plurality of FETs to reduce the input voltage to a first stage output voltage; and

a buck-type voltage regulator (VR) stage to convert the first stage output voltage to a second stage output voltage lower than the first stage output voltage.

2. The multi-stage power delivery network of claim 1, wherein the IC is a microprocessor, the input voltage is approximately 12V, series switch module includes CMOS FETs and the first stage output voltage is between approximately 2.8 V and approximately 3.3 V.

3. The multi-stage power delivery network of claim 1, wherein the series switch module is mounted to a printed circuit board on which a package of the IC is mounted.

4. The multi-stage power delivery network of claim 3, wherein the plurality of capacitors comprise discrete capacitors mounted to the printed circuit board.

5. The multi-stage power delivery network of claim 3, wherein the plurality of capacitors comprise capacitors embedded into the printed circuit board.

6. The multi-stage power delivery network of claim 1, wherein both the series switch module and the VR are integrated in CMOS and placed in a package of the IC.

7. The multi-stage power delivery network of claim 6, wherein the plurality of capacitors comprise discrete capacitors mounted to the printed circuit board.

8. The multi-stage power delivery network of claim 6, wherein the plurality of capacitors comprise MIM capacitors embedded into the package.

9. An electronic device comprising:

a microprocessor in a package coupled to a printed circuit board;

a switched capacitor divider (SCD) to convert an input power supply voltage to a first output power supply voltage, the SCD including series switches coupled to a plurality of capacitors, wherein the series switches are integrated onto the package; and

a voltage regulator (VR) to convert the first output power supply voltage to a second output power supply voltage, wherein the VR is integrated onto the package and the second output power supply voltage is coupled with the microprocessor to power the microprocessor.

10. The electronic device of claim 9, wherein the plurality of capacitors are integrated with the package.

11. The electronic device of claim 10, wherein the plurality of capacitors are MIM capacitors integrated with a silicon substrate of the series switches.

12. The electronic device of claim 10, wherein the plurality of capacitors are MIM capacitors embedded into the package.

13. The electronic device of claim 10, wherein the plurality of capacitors include at least one of discrete capacitors mounted to the printed circuit board or MIM capacitors embedded into the printed circuit board.

14. The electronic device of claim 10, wherein the series switches further comprise:

a plurality of CMOS FETs configured in series with drain terminals coupled with source terminals and connected across the input power supply voltage, wherein alternating ones of the plurality have gate terminals coupled together to form a first and second pair of gate coupled FETs, and wherein the first pair of gate coupled FETs is configured to be switched between a low state and a high state within a switching cycle while the second pair of gate coupled FETs is configured to be switched to a state opposite the first pair of gate coupled FETs; and

wherein the plurality of capacitors further comprise;

a first capacitor coupled to a drain terminal of each of the first pair of gate coupled FETs; and

a second capacitor coupled to a drain terminal of each of the second pair of gate coupled FETs.

15. A method of delivering power to an integrated circuit (IC), the method comprising:

converting an input voltage to a first output voltage with a switched capacitor divider (SCD) including series switches and a plurality of capacitors coupled with the series switches;

converting the first output voltage with a voltage regulator (VR) to a second output voltage; and

delivering the second output voltage to the IC, wherein the switch network, VR and IC are integrated into one package.

16. The method of claim 15, wherein the capacitors are embedded in the package.

17. The method of claim 15, the method further comprising:

alternately switching ones of the plurality of capacitors at a duty cycle with the series switches, the series switches comprising a plurality of CMOS FETs configured in series with drain terminals coupled with source terminals and connected across the input voltage, the plurality of CMOS FETs contained in a module having a plurality of pinouts coupled with the plurality of CMOS FET drain terminals and with the capacitors connected across the voltage input.

18. The method of claim 17, wherein the capacitors are MIM capacitors monolithically integrated with the FETs of the switch network.

19. The method of claim 15, wherein the capacitors are discrete capacitors mounted to the printed circuit board.

20. The method of claim 15, wherein the VR is a buck-type converter including at least one of a stand-alone or a coupled inductor.