LCD CONTROLLER WITH LOW POWER MODE
First Claim
1. An LCD controller, comprising:
- a host interface control block for providing a connection between the LCD controller and a master controller, the master controller initiating a low power mode of operation through the host interface control block;
a plurality of input/output pins, wherein at least a first portion thereof provide a connection to at least one LCD display;
an LCD static display controller for driving the at least one LCD display connected to the first portion of the plurality of input/output pins in a static display mode responsive to entry of the LCD controller into the low power mode of operation;
a real time clock circuit for providing a clock signal to the LCD static display controller in the low power mode of operation; and
power circuitry for selectively disabling a regulated voltage provided to circuitry in the LCD controller not required to operate the LCD static display controller and the real time clock circuitry in the low power mode of operation.
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Accused Products
Abstract
An LCD controller comprises a host interface control block for providing a connection between the LCD controller and a master controller. The master controller initiates a low power mode of operation for the LCD controller through the host interface control block. At least a portion of a plurality of input/output pins provide a connection to at least one LCD display for the LCD controller. An LCD static display controller within the LCD controller drives the at least one LCD display in a static display mode responsive to entry of the LCD controller into the low power mode of operation. A real time clock provides a clock signal to the LCD static display controller in the low power mode of operation. Power circuitry within the LCD controller selectively disables a regulated voltage provided to circuitry in the LCD controller that is not required to operate the LCD static display controller and the real time clock circuit in the low power mode of operation.
30 Citations
19 Claims
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1. An LCD controller, comprising:
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a host interface control block for providing a connection between the LCD controller and a master controller, the master controller initiating a low power mode of operation through the host interface control block; a plurality of input/output pins, wherein at least a first portion thereof provide a connection to at least one LCD display; an LCD static display controller for driving the at least one LCD display connected to the first portion of the plurality of input/output pins in a static display mode responsive to entry of the LCD controller into the low power mode of operation; a real time clock circuit for providing a clock signal to the LCD static display controller in the low power mode of operation; and power circuitry for selectively disabling a regulated voltage provided to circuitry in the LCD controller not required to operate the LCD static display controller and the real time clock circuitry in the low power mode of operation. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An LCD controller, comprising:
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a host interface control block for providing a connection between the LCD controller and a master controller, the master controller initiating a low power mode of operation through the host control block; a plurality of input/output pins, wherein at least a first portion thereof provide a connection to at least one LCD display; an LCD static display controller for driving the at least one LCD display connected to the first portion of the plurality of input/output pins in a static display mode responsive to entry of the LCD controller into the low power mode of operation; port match logic for comparing a value on at least one of the plurality of input/output pins to a predetermined value while the LCD controller is within the low power mode of operation and generating an interrupt when the value on the at least one of the plurality of input/output pins does not equal the predetermined value; a real time clock circuit for providing a clock signal to the LCD static display controller and the port match logic in the low power mode of operation; and power circuitry for selectively disabling a regulated voltage provided to circuitry in the LCD controller not required to operate the LCD static display controller, the port match logic and the real time clock circuit in the low power mode of operation. - View Dependent Claims (9, 10, 11, 12)
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13. A method for operating an LCD controller in a low power mode of operation, comprising the steps of:
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receiving a control input at the LCD controller from a master controller; initiating a low power mode of operation responsive to receipt of the control input from the master; generating a clock signal in the low power mode of operation; driving at least one LCD display in a static display mode responsive to entry of the LCD controller into the low power mode of operation and the clock signal; selectively disabling a regulated voltage provided to circuitry in the LCD controller not required to operate the LCD display in the low power mode of operations. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification