COMBINATION MEMORY DEVICE AND SEMICONDUCTOR DEVICE

• US 20090323434A1
• Filed: 06/16/2009
• Published: 12/31/2009
• Est. Priority Date: 06/26/2008
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: YAMANE, Ichiro, KOMATSU, Shigeyuki
• Granted Patent: US 8,081,525 B2
• Time in Patent Office: Days
• US Class Current: 365/189.2
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/18 Peripheral circuit regions
• CPC Class Codes: H10B 20/34 Source electrode or drain electrode programmed
• CPC Class Codes: H10B 20/65 of memory structures of the ROM only type

Abstract

A combination memory device including a static random access memory (SRAM) and a read only memory (ROM) comprises first memory cells and second memory cells arranged in rows and columns, in which each of the first memory cells includes an SRAM cell and a ROM cell and is arranged adjacent to at least one of the second memory cells, and each of the second memory cells includes an SRAM cell and does not include a ROM cell.

Claims

1. A combination memory device including a static random access memory (SRAM) and a read only memory (ROM), said combination memory device comprising

first memory cells and second memory cells arranged in rows and columns,

wherein each of said first memory cells includes an SRAM cell and a ROM cell and is arranged adjacent to at least one of said second memory cells, and

each of said second memory cells includes an SRAM cell and does not include a ROM cell.

2. The combination memory device according to claim 1, further comprising:

a word line which is provided for each row for selecting said SRAM cells and said ROM cells placed in the row;

a first bit line and a second bit line each of which is provided for each column, for reading data from said SRAM cells placed in the column and for writing data on said SRAM cells; and

a third bit line which is provided for each column for reading data from said ROM cells placed in the column.

3. The combination memory device according to claim 2,

wherein said SRAM cell includes:

a first inverter having an input terminal connected to a first node, and an output terminal connected to a second node;

a second inverter having an input terminal connected to the second node, and an output terminal connected to the first node;

a first transistor having a first terminal connected to the first node, a second terminal connected to said first bit line, and a gate connected to said word line, said first terminal being one of a drain and a source, said second terminal being the other of the drain and the source; and

a second transistor having a first terminal connected to the second node, a second terminal connected to said second bit line, and a gate connected to said word line, said first terminal being one of a drain and a source, said second terminal being the other of the drain and the source, and

wherein said ROM cell includes a third transistor having a source connected to a ground (GND), and a gate connected to said word line, and

said ROM cell outputs, to said third bit line, data determined depending on whether or not a contact is included, said contact connecting said drain of said third transistor to said third bit line.

4. The combination memory device according to claim 3,

wherein a part of a region of said third transistor included in each of said first memory cells is placed in a region of corresponding one of said second memory cells arranged adjacent to said first memory cell.

5. The combination memory device according to claim 4,

wherein in said first memory cells and said second memory cells, said first and second inverters and said first and second transistors are sequentially placed in order, starting from a first end to a second end, in a column direction,

each of said first memory cells and said second memory cells is placed so that:

the first end faces the first end of corresponding one of said first memory cells and said second memory cells adjacent to each other in the column direction;

or the second end faces the second end of corresponding one of said first memory cells and said second memory cells adjacent to each other in the column direction, and

the part of the region of said third transistor included in each of said first memory cells is placed on a boundary between said first memory cells and said second memory cells on the second end.

6. The combination memory device according to claim 5,

wherein said first transistor, said second transistor, and said third transistor, each of which is included in said first memory cells and said second memory cells placed in each row, are placed alongside in the row direction,

said first inverter and said second inverter included in said first memory cells and said second memory cells placed in each row are placed alongside in the row direction,

said gates of said first transistor, said second transistor, and said third transistor included in said first memory cells and second memory cells placed in each row, are formed of a common polysilicon line,

said first terminals of said first transistors included in said first memory cells and said second memory cells adjacent to each other at the second ends are formed of a first diffusion region placed on the boundary on the second ends, and said first terminal of said second transistors are formed of a second diffusion region placed on the boundary on the second ends, said first diffusion region and said second diffusion region being shared by corresponding first terminals,

said source of said ROM cell is formed of a third diffusion region shared by the GNDs of said first inverter and said second inverter placed adjacent to each other in the row direction, and

a fourth diffusion region that is said drain of said third transistor is placed alongside with said first diffusion region and said second diffusion region in the row direction on the boundary between on the second ends.

7. The combination memory device according to claim 1,

wherein each of said first memory cells and each of said second memory cells are placed alternately in the row direction and in the column direction.

8. The combination memory device according to claim 3,

wherein said third bit line includes fourth bit lines, and

said ROM cell outputs data of plural bits via said fourth bit lines, by outputting data to each of said fourth bit lines, the data determined depending on whether or not said contact is included, said contact connecting said drain of said third transistor to each of said fourth bit lines.

9. The combination memory device according to claim 8,

wherein said ROM cell outputs, to said fourth bit lines, data of plural bits which is determined depending on:

whether or not said contact is included; and

to which one of said fourth bit lines said contact connects said drain of said third transistor, said ROM cell including only one of said contact at most.

10. The combination memory device according to claim 9,

wherein each of said first memory cells and each of said second memory cells are placed alternately in the row direction and in the column direction,

said fourth bit lines are three bit lines, and

said ROM cell outputs, to said fourth bit lines that are the three bit lines, 3-bit data in four patterns determined depending on:

whether or not said contact is included; and

to which one of said three fourth bit lines said contact connects said drain of said third transistor, said ROM cell including only one of said contact at most.

11. The combination memory device according to claim 8,

wherein said first bit line and said second bit line are formed of a first metal wiring layer, and

said fourth bit lines are formed of a second metal wiring layer that is different from the first metal wiring layer.

12. The combination memory device according to claim 8, further comprising:

sense amplifiers provided for each of said fourth bit lines, each of said sense amplifiers amplifying data of a corresponding one of said fourth bit lines; and

an encoding circuit which encodes the data of plural bits so that the number of bits decreases, the data having been amplified by said sense amplifiers.

13. The combination memory device according to claim 2, further comprising:

a RAM column selection circuit which selects, from among sets of said first bit lines and said second bit lines, a set corresponding to an address inputted from outside;

a RAM reading circuit which amplifies a signal of the set of said first bit lines and said second bit lines selected by said RAM column selection circuit;

a RAM writing circuit which provides the set of said first bit lines and said second bit lines that has been selected by said RAM column selection circuit with a signal corresponding to writing data;

a ROM column selection circuit which selects, from among said third bit lines, said third bit line corresponding to the address; and

a ROM reading circuit which amplifies a signal of said third bit line selected by said ROM column selection circuit,

wherein said RAM column selection circuit selects none of the sets of said first bit lines and said second bit lines during a time when one of said third bit lines is selected by said ROM column selection circuit, and

said ROM column selection circuit selects none of said third bit lines during a time when one of the sets of said first bit lines and said second bit lines is selected by said RAM column selection circuit.

14. The combination memory device according to claim 2, further comprising:

a timing circuit which activates said word line at a time of;

data writing onto said SRAM cell;

data reading from said SRAM cell; and

data reading from said ROM cell, for different amount times.

15. The combination memory device according to claim 2,

wherein said ROM cell outputs, to said third bit line, data determined depending on:

(i) whether or not a third transistor having a source to which a GND is connected, a gate to which said word line is connected, and said third bit line to which a drain is connected, is included, or

(ii) whether or not said third transistor and a diffusion region are included, said third transistor having a gate to which said word line is connected and said third bit line to which a drain is connected, said diffusion region connecting the GND to said source of said third transistor.

16. A semiconductor device comprising

a flash memory;

and

a combination memory device in claim 1,

wherein said ROM included in said combination memory device stores a loader program for writing data onto said flash memory.