SEMICONDUCTOR MEMORY DEVICE AND RESET CONTROL CIRCUIT OF THE SAME

• US 20090323442A1
• Filed: 12/30/2008
• Published: 12/31/2009
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Song, Choung Ki
• Granted Patent: US 7,948,815 B2
• Time in Patent Office: Days
• US Class Current: 365/191
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

The semiconductor memory device includes a reset control circuit that monitors a reset signal at an enablement time point of the reset signal input and outputs monitoring signals corresponding to a state of the reset signal. The reset control unit also enables and outputs a reset control signal when the states of the monitoring signals are equal, and ends the monitoring of the reset signal in synchronization with the enablement of the reset control signal. An internal circuit receives the reset control signal, and the reset control signal controls the initialization of the internal circuit. When the reset signal maintains the enablement state for a predetermined period, the reset control signal is enabled, making it possible to prevent reset malfunction associated with a glitch occurring in the reset signal.

Claims

1. A semiconductor memory device comprising:

a reset control circuit;

monitoring a state of a reset signal in synchronization with an enablement time point of the reset signal and outputting monitoring signals corresponding to a state of the reset signal,

enabling and outputting a reset control signal, wherein the reset control signal is enabled when states of the monitoring signals are equal, and

stopping the monitoring of the reset signal in synchronization with the enablement of the reset control signal; and

an internal circuit receiving the reset control signal, wherein an initialization of the internal circuit is controlled by the reset control signal.

2. The semiconductor memory device as set forth in claim 1, wherein the reset control circuit generates an internal clock signal toggled in synchronization with the enablement of the reset signal and outputs the monitoring signals according to the state of the reset signal in synchronization with a toggling of the internal clock signal.

3. The semiconductor memory device as set forth in claim 2, wherein the internal clock signal is toggled two or more in number and the reset control signal is enabled when states of the monitoring signals corresponding to the toggling of the internal clock signal are equal.

4. The semiconductor memory device as set forth in claim 3, wherein the reset control circuit receives the reset control signal as feedback so as to stop the toggling of the internal clock signal in synchronization with the enablement of the reset control signal.

5. The semiconductor memory device as set forth in claim 1, wherein the reset control circuit receives an external clock signal and outputs the monitoring signals according to the state of the reset signal in synchronization with a toggling of the external clock signal.

6. The semiconductor memory device as set forth in claim 5, wherein the reset control signal is enabled when states of the monitoring signals corresponding to the two or more toggling of the external clock signal are equal.

7. The semiconductor memory device as set forth in claim 1, wherein the reset control circuit receives the reset control signal as feedback so as to initialize the monitoring signals when both the reset signal and the reset control signal are disabled.

8. The semiconductor memory device as set forth in claim 1, wherein the reset signal is a signal which an external reset signal input from outside the semiconductor memory device is buffered.

9. A reset control circuit of a semiconductor memory device comprising:

an oscillator receiving a reset signal and generating an internal clock signal according to the reset signal;

a reset signal monitor unit monitoring a state of the reset signal in synchronization with a toggling of the internal clock signal and outputting monitoring signals corresponding to the state of the reset signal;

a reset control signal output unit outputting a reset control signal controlling an initialization of an internal circuit of the semiconductor memory device according to the monitoring signals; and

a monitor initialization unit logically combining the reset signal and the reset control signal to output a monitor initialization signal for initializing the reset signal monitor unit.

10. The reset control circuit of the semiconductor memory device as set forth in claim 9, wherein the oscillator toggles the internal clock signal in synchronization with an enablement of the reset signal.

11. The reset control circuit of the semiconductor memory device as set forth in claim 10, wherein the oscillator receives the reset control signal as feedback to stop the toggling of the internal clock signal in synchronization with the enablement of the reset control signal.

12. The reset control circuit of the semiconductor memory device as set forth in claim 11, wherein the oscillator toggles the internal clock signal when a state of the reset signal is changed and stops the toggling of the internal clock signal when the state of the reset control signal is changed.

13. The reset control circuit of the semiconductor memory device as set forth in claim 11, wherein the oscillator toggles the internal clock signal when the state of the reset signal is not equal to the state of the reset control signal and stops the toggling of the internal clock signal when the state of the reset signal is equal to the state of the reset control signal.

14. The reset control circuit of the semiconductor memory device as set forth in claim 10, wherein the oscillator has a ring oscillator structure that selectively toggles the internal clock signal according to a logical combination of the reset signal and the reset control signal.

15. The reset control circuit of the semiconductor memory device as set forth in claim 9, wherein the reset signal monitor unit outputs the monitoring signals according to the state of the reset signal in synchronization with edges of the internal clock signal, wherein the edge of the internal clock signal is one of a rising edge or a falling edge.

16. The reset control circuit of the semiconductor memory device as set forth in claim 15, wherein the reset signal monitor unit comprises a shift register, wherein the shift register shifts the state of the reset signal in synchronization with the edges of the internal clock signal and outputs the monitoring signals corresponding to the shifted states by the shift register.

17. The reset control circuit of the semiconductor memory device as set forth in claim 15, wherein the reset signal monitor unit comprises:

a plurality of serially connected flip flops, the plurality of serially connected flip flops comprising;

a first flip flop outputting a first enable signal corresponding to the state of the reset signal in synchronization with the edge of the internal clock signal; and

a plurality of second flip flops sequentially outputting second enable signals corresponding to an output state of the flip flops in a previous stage in synchronization with the edge of the internal clock signal,

wherein the first and the second enable signals correspond to the monitoring signals.

18. The reset control circuit of the semiconductor memory device as set forth in claim 9, wherein the reset control signal output unit enables the reset control signal when states of the monitoring signals are equal.

19. The reset control circuit of the semiconductor memory device as set forth in claim 9, wherein the monitor initialization unit logically combines the reset signal and the reset control signal to determine the enablement of the monitor initialization signal, wherein the monitor initialization signal is enabled when both the reset signal and the reset control signal are equal to a disablement state.

20. A reset control circuit of a semiconductor memory device comprising:

a reset signal monitor unit receiving an external clock signal and a reset signal and monitoring a state of the reset signal in synchronization with the external clock signal and outputting monitoring signals corresponding to the state of the reset signal;

a reset control signal output unit outputting the reset control signal controlling an initialization of an internal circuit of the semiconductor memory device according to the monitoring signals; and

a monitor initialization unit logically combining the reset signal and the reset control signal to output a monitor initialization signal for initializing the reset signal monitor unit.

21. The reset control circuit of the semiconductor memory device as set forth in claim 20, wherein the reset signal monitor unit outputs the monitoring signals according to the reset signal in synchronization with edges of the external clock signal, wherein the edge of the internal clock signal is one of a rising edge or a failing edge.

22. The reset control circuit of the semiconductor memory device as set forth in claim 21, wherein the reset signal monitor unit comprises a shift register, wherein the shift register shifts the state of the reset signal in synchronization with the edges of the external clock signal and the monitoring signals corresponds to the shifted states by the shift register.

23. The reset control circuit of the semiconductor memory device as set forth in claim 21, wherein the reset signal monitor unit comprises a plurality of serially connected flip flops, the plurality of serially connected flip flops comprising:

a first flip flop outputting a first enable signal corresponding to the state of the reset signal in synchronization with the edge of the external clock signal; and

a plurality of second flip flops sequentially outputting second enable signals corresponding to an output state of the flip flops in a previous stage in synchronization with the edge of the external clock signal,

wherein the first and the second enable signals correspond to the monitoring signals.

24. The reset control circuit of the semiconductor memory device as set forth in claim 20, wherein the reset control signal output unit enables the reset control signal when states of the monitoring signals are equal.

25. The reset control circuit of the semiconductor memory device as set forth in claim 20, wherein the monitor initialization unit logically combines the reset signal and the reset control signal to enable the monitor initialization signal when both the reset signal and the reset control signal are equal to a disablement state.