MEMORY OPERATION TESTING

• US 20090323446A1
• Filed: 06/30/2008
• Published: 12/31/2009
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: ZHANG, SHAYAN, SNYDER, MICHAEL D., HIGMAN, JACK M.
• Granted Patent: US 7,852,692 B2
• Time in Patent Office: Days
• US Class Current: 365/201
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing

Abstract

Test circuitry for determining whether a memory can operate at a lower operating voltage. The test circuitry includes a sense circuit having a delayed sensing characteristic as compared to other sense amplifier circuits of the memory. With this circuitry the test circuitry can determine if the sense circuit can provide valid data under more severe sensing conditions. In one example, the sense circuit includes a delay circuit in the sense enable signal path. If sense circuit can provide data at more server operating conditions, then the memory operating voltage can be lowered.

Claims

1. A method for operating a memory wherein the memory includes an array of memory cells, the method comprising:

providing a first operating voltage to a first portion of the memory, the first portion including a first set of memory cells of the array, wherein the memory includes a first plurality of sense amplifier circuits coupled to the first set of memory cells;

testing a second set of memory cells of the array of the memory to determine if the second set can operate at a lower operating voltage than the first operating voltage, wherein the memory includes a diagnostic sense circuit coupled to at least some of the second set of cells, the diagnostic sense circuit having a delayed sensing characteristic as compared to the first plurality of sense amplifier circuits;

wherein the testing is performed while the operating voltage is provided to the first portion of the memory and the first set of memory cells are operable to store data, the testing further includes using the diagnostic sense circuit to sense data from at least one cell of the second set of cells, wherein the testing includes reading a stored value of the at least one cell and determining if valid data is read.

2. The method of claim 1, wherein the reading a stored value of the at least one cell and determining if valid data is read further includes determining whether an accurate representation of a logic state of the at least one cell read by the diagnostic sense circuit is provided to a latch input at a predetermined time relative to a first clock edge.

3. The method of claim 1, wherein the testing further includes performing a write verification test on at least one of the second set of memory cells with a write voltage is applied to the at least one cell from a word line during a write, wherein the write voltage is less than a second write voltage applied to memory cells of the first set by a second word line.

4. The method of claim 3 further comprising:

outputting an asserted word line signal on the word line by a word line driver for writing to the at least one of the second set of memory cells;

reducing a voltage of the asserted word line signal prior to the asserted word line signal being provided to the at least one of the second set of memory cells.

5. The method of claim 1, wherein the testing further comprising:

performing a read verification test on at least one cell of the second set of cells, wherein the read verification test includes powering the at least one cell at a test voltage while powering cells of the first set at the operating voltage, wherein test voltage is less than the operating voltage.

6. The method of claim 1 further comprising:

if the testing determines that the second set can operate at the lower operating voltage than the first operating voltage, changing the first operating voltage provided to the first portion of the memory to the lower operating voltage.

7. The method of claim 6 further comprising:

if the testing determines that the second set can operate at the lower operating voltage than the first operating voltage, testing for a second time, the second set of cells of the array of the memory to determine if the second set can operate at a second lower operating voltage, wherein the second lower operating voltage is lower than the lower operating voltage;

if the second testing determines that the second set can operate at the second lower operating voltage, changing the lower operating voltage provided to the first portion of the memory to the second lower operating voltage.

8. The method of claim 1, wherein the diagnostic sense circuit having a delayed sensing characteristic compared to the first plurality of sense amplifier circuits is further characterized as the diagnostic sense circuit having a delay circuit that delays an assertion of a sense enable signal to a sense amplifier of the diagnostic sense circuit as compared to the assertion of a sense enable signal being provided to a sense amplifier of the first plurality of sense amplifier circuits.

9. The method of claim 1 further comprising:

if the testing determines that the second set can not operate at the lower operating voltage than the first operating voltage, changing the first operating voltage provided to the first portion of the memory to a higher operating voltage.

10. A circuit, comprising:

an array of memory cells;

a first plurality of sense circuits coupled to a first set of memory cells of the array, each of the first plurality of sense circuits including a sense amplifier for reading a data value of a cell of the first set coupled to the sense circuit during a read operation, each of the first plurality of sense circuits including an output for providing an indication of a data value of a cell of the first set coupled to sense circuit during a read operation as determined by the sense amplifier of the sense circuit;

a diagnostic sense circuit coupled to a second set of memory cells of the array, the diagnostic sense circuit including an output for providing an indication of a data value of a cell of the second set coupled to diagnostic sense circuit during a read operation, wherein the diagnostic sense circuit is characterized as having a delayed sensing characteristic with respect to the sense circuits of the first plurality of sense circuits in providing a data value of a cell during a read operation.

11. The circuit of claim 10 wherein:

each of the first plurality of sense circuits includes an input to receive a sense enable signal for activating the sense amplifier of the sense circuit during a read;

the diagnostic sense circuit includes an input to receive the sense enable signal,

the delayed sensing characteristic is characterized in that the diagnostic sense circuit includes a delay element in a path between the input and the sense amplifier of the diagnostic sense circuit such that time period for activation of the sense amplifier of the diagnostic sense circuit from the assertion of the sense enable signal is greater than the time period for activation of the sense amplifier of the first plurality of sense circuits from the assertion of the sense enable signal.

12. The circuit of claim 11, wherein the delay element is programmable.

13. The circuit of claim 10 wherein:

each of the first plurality of sense amplifiers is coupled to at least one bit line for receiving an indication of a value of a cell during a read operation of the cell;

the diagnostic sense circuit includes a logic gate couple to the at least one bit line for receiving an indication of a value of a cell during a read operation of a cell, wherein the delayed sensing characteristic of the diagnostic sense circuit is characterized as the logic gate being configured to provide a data value of cell during a read operation at a later time than the sense amplifiers of the first plurality of sense circuits.

14. The circuit of claim 10 further comprising:

a determination circuit operably coupled to the diagnostic sense circuit to determine whether the sense diagnostic circuit provides valid data during a read operation.

15. The circuit of claim 14 further comprising:

controlling circuitry coupled to the determination circuit for adjusting an operating voltage being supplied to a memory array, wherein the controlling circuitry lowers the operating voltage in response to a determination that the memory can operate at a lower operating voltage, wherein the determination that the memory can operate at a lower operating voltage is based on the determination circuit determining that the diagnostic sense circuit provides valid data during a read operation.

16. The circuit of claim 14 further comprising:

a latch circuit having a first input coupled to receive data from the diagnostic sense circuit, a second input coupled to receive a clock signal, and an output coupled to the determination circuit;

wherein the determination circuit determines whether the diagnostic sense circuit provides valid data by comparing the output of the latch circuit to a value written to the cell being read.

17. The circuit of claim 14 further comprising:

a latch circuit having a first input coupled to receive data from the sense diagnostic circuit, a second input coupled to receive a clock signal, and an output coupled to the determination circuit;

wherein the diagnostic sense circuit provides valid data during a read operation if the first input of a latch circuit receives data from the diagnostic sense signal prior to a clock edge received at the second input, wherein the latch circuit is configures to latch at its output a logic value of its first input at the clock edge.

18. The circuit of claim 10 wherein:

the array includes a first column of cells and a plurality of columns of cells, wherein each cell of first column and each cell of the plurality of columns of cells include a bias input for receiving an operating voltage for powering the cell;

the circuit further comprises;

a voltage regulator having an output for providing operating power to each bias input;

a voltage reduction device coupled between the output of the voltage regulator and the bias inputs of the cells of the first column to selectively reduce the voltage at the bias input of the cells of the first column with respect to the voltage at the inputs of the cells of the plurality of columns.

19. The circuit of claim 10 wherein:

the array includes a first row of cells and a plurality of rows of cells, wherein each cell of first row is coupled to a first word line, and each cell of each row of the plurality of rows is coupled to a word line of a first plurality of word lines associated with that row;

a word line driver including a first output coupled to the first word line, the word line driver including a first plurality of outputs, each output of the first plurality of outputs coupled to a word line of the first plurality;

a word line voltage reduction device coupled between the first output of the word line driver and the first row of cells for reducing the voltage on the first word line when a word line signal is asserted with respect to the voltages on the plurality of word lines when word line signals are asserted.

20. A method, comprising:

asserting a sense enable signal on a sense enable line;

providing the asserted sense enable signal to a first plurality of sense amplifiers of a memory, each of the first plurality of sense amplifiers is coupled to a column of memory cells of a plurality of memory cells of an array;

delaying the asserted sense enable signal so as to provide the asserted sense enable signal to a second sense amplifier after the providing the asserted sense enable signal to the first plurality of sense amplifiers;

providing an output signal of the second sense amplifier to an input of a latch circuit, the output signal of the second sense amplifier provided in response to the asserted sense enable signal being provided to the second sense amplifier;

latching at an output of the latch circuit a value of the input of the latch circuit at a clock edge;

determining whether the input of the latch circuit received valid data from the output signal prior to the latching by comparing the output of the latch circuit to a second value.