Dual Mode Memory System for Reducing Power Requirements During Memory Backup Transition

• US 20090323452A1
• Filed: 06/25/2008
• Published: 12/31/2009
• Est. Priority Date: 06/25/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Elliott, John C., Lucas, Gregg S., Cagno, Brian J.
• Granted Patent: US 8,040,750 B2
• Time in Patent Office: Days
• US Class Current: 365/227
• CPC Class Codes: G11C 5/141 Battery and back-up supplies

Abstract

A controller of a memory system is configured to reduce power requirements during memory backup transition. When transitioning to backup mode, the memory system controller performs a number of power saving techniques. The controller may change a number of configuration settings in the volatile memory system, such as reducing output driver strength, increasing differential impedance, increasing on-die termination, disabling receiver input circuitry, and disconnecting the termination voltage network. The controller may also assert a hard reset to the storage controller system to significantly reduce the load and allow the voltage regulator to continue to provide power to the memory system for a longer period of time.

Claims

1. A computer program product comprising a computer recordable medium having a computer readable program recorded thereon, wherein the computer readable program, when executed on a computing device, causes the computing device to:

transition to memory backup mode to store data from a volatile memory to a non-volatile memory responsive to a power event;

reduce power requirements for the volatile memory responsive to transitioning to memory backup mode; and

store data from the volatile memory to the non-volatile memory using power provided by a hold-up voltage source.

2. The computer program product of claim 1, wherein reducing power requirements for the volatile memory comprises:

reducing output driver strength for the volatile memory.

3. The computer program product of claim 1, wherein reducing power requirements for the volatile memory comprises:

changing differential impedance within the volatile memory to a maximum acceptable value.

4. The computer program product of claim 1, wherein reducing power requirements for the volatile memory comprises:

changing on-die termination within the volatile memory to a maximum acceptable value.

5. The computer program product of claim 1, wherein reducing power requirements for the volatile memory comprises:

disabling receiver input circuitry within the volatile memory.

6. The computer program product of claim 1, wherein the data processing system comprises a storage controller having a power supply, a storage controller, and a memory system, wherein the memory system comprises the volatile memory and the non-volatile memory, wherein the power supply provides power to the storage controller and the memory system, wherein the memory system comprises the hold-up voltage source, wherein the hold-up voltage source provides power to the memory system responsive to the power event, and wherein the computer readable program further causes the computing device to:

assert a reset to the storage controller responsive to transitioning to memory backup mode.

7. A method, in a data processing system, for reducing power requirements during memory backup transition, the method comprising:

responsive to a power event, transitioning to memory backup mode to store data from a volatile memory to a non-volatile memory;

responsive to transitioning to memory backup mode, reducing power requirements for the volatile memory; and

storing data from the volatile memory to the non-volatile memory using power provided by a hold-up voltage source.

8. The method of claim 7, wherein reducing power requirements for the volatile memory comprises:

reducing output driver strength for the volatile memory.

9. The method of claim 7, wherein reducing power requirements for the volatile memory comprises:

changing differential impedance within the volatile memory to a maximum acceptable value.

10. The method of claim 7, wherein reducing power requirements for the volatile memory comprises:

changing on-die termination within the volatile memory to a maximum acceptable value.

11. The method of claim 7, wherein reducing power requirements for the volatile memory comprises:

disabling receiver input circuitry within the volatile memory.

12. The method of claim 7, wherein the data processing system comprises a storage controller having a power supply, a storage controller, and a memory system, wherein the memory system comprises the volatile memory and the non-volatile memory, wherein the power supply provides power to the storage controller and the memory system, wherein the memory system comprises the hold-up voltage source, and wherein the hold-up voltage source provides power to the memory system responsive to the power event.

13. The method of claim 12, further comprising:

responsive to transitioning to memory backup mode, asserting a reset to the storage controller.

14. The method of claim 7, wherein the hold-up voltage source is a super capacitor.

15. The method of claim 7, wherein the power event is an early power off warning.

16. A memory system comprising:

a controller, wherein the controller is configured to detect a power event from a power supply that provides power to a storage controller and the memory system;

a volatile memory;

a non-volatile memory; and

a hold-up voltage source, wherein the hold-up voltage source is configured to provide power to the memory system responsive to the power event,

wherein the controller is configured to transition to memory backup mode to store data from the volatile memory to the non-volatile memory responsive to a power event, reduce power requirements for the volatile memory responsive to transitioning to memory backup mode, and store data from the volatile memory to the non-volatile memory using power provided by a hold-up voltage source.

17. The memory system of claim 16, wherein reducing power requirements for the volatile memory comprises at least one of reducing output driver strength for the volatile memory, changing differential impedance within the volatile memory to a maximum acceptable value, changing on-die termination within the volatile memory to a maximum acceptable value, or disabling receiver input circuitry within the volatile memory.

18. The memory system of claim 16, wherein the controller is configured to assert a reset to the storage controller responsive to transitioning to memory backup mode.

19. The memory system of claim 16, wherein the hold-up voltage source is a super capacitor.

20. The memory system of claim 16, wherein the power event is an early power off warning.