SYSTEM AND METHOD OF PROVIDING ELECTRICAL ISOLATION

• US 20090323717A1
• Filed: 06/30/2008
• Published: 12/31/2009
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Landry, D. Matthew, Callahan, Phillip A.
• Granted Patent: US 7,804,859 B2
• Time in Patent Office: Days
• US Class Current: 370/463
• CPC Class Codes: H03K 17/689 with galvanic isolation between the control circuit and the output circuit H03K17/78 takes precedence
• CPC Class Codes: H04L 12/40039 Details regarding the setting of the power status of a node according to activity on the bus

Abstract

In a particular embodiment, a system includes an input/output (I/O) interface adapted to couple to a network cable to receive power and data and includes a physical transport layer (PHY) circuit including multiple channels coupled to the I/O interface. The PHY circuit is adapted to send data to and receive data from a network device via the multiple channels. The system further includes a multiplexer circuit coupled to the PHY circuit to multiplex data from the multiple channels into a multiplexed data stream and includes an isolation barrier circuit coupled to the multiplexer circuit and to a particular circuit. The isolation barrier is adapted to electrically isolate a particular circuit from the multiplexer circuit, the PHY circuit, and the I/O interface.

Claims

1. A system comprising:

an input/output (I/O) interface adapted to couple to a network cable to receive power and data;

a physical transport layer (PHY) circuit including multiple channels coupled to the I/O interface, the PHY circuit adapted to send data to and receive data from a network device via the multiple channels;

a multiplexer circuit coupled to the PHY circuit to multiplex data from the multiple channels into a multiplexed data stream; and

an isolation barrier circuit coupled to the multiplexer circuit and to a particular circuit, the isolation barrier adapted to electrically isolate the particular circuit from the multiplexer circuit, the PHY circuit, and the I/O interface.

2. The system of claim 1, further comprising a powered device (PD) control circuit coupled to the multiplexer circuit to receive control signals from the particular circuit or from the PHY circuit.

3. The system of claim 2, wherein the PD control circuit and the PHY circuit receive power from the I/O interface.

4. The system of claim 2, wherein the PD control circuit comprises:

powered device (PD) detection logic to provide a device signature to the network device during a PD detection process;

PD classification logic to provide a power classification signature to the network device during a PD classification process; and

logic to control a regulated power supply to provide operating power to the particular circuit during operation.

5. The system of claim 1, wherein the PHY circuit is adapted to negotiate a data link to the network device independent from the particular circuit and other circuitry.

6. The system of claim 5, wherein the PHY circuit is adapted to negotiate the data link using one of a vendor specific identifier and a vendor specific link negotiation protocol.

7. The system of claim 1, wherein the particular circuit includes a power saving mode to disable selected circuitry during periods of inactivity.

8. The system of claim 7, wherein the PHY circuit is adapted to receive data from the I/O interface and to trigger the particular circuit to enter an operating mode in response to receiving the data.

9. A circuit device comprising:

a physical transport layer (PHY) circuit including multiple channels coupled to an I/O interface, the PHY circuit adapted to send data to and receive data from a network device via the multiple channels;

a multiplexer circuit coupled to the PHY circuit to multiplex data from the multiple channels onto a bidirectional input/output (I/O) interface bus; and

a digital isolation barrier circuit coupled to the bidirectional I/O interface bus and adapted to electrically isolate processing logic from the multiplexer circuit, the PHY circuit, and the I/O interface.

10. The circuit device of claim 9, wherein the bidirectional I/O interface bus comprises one of a media independent interface (MII) bus, a Gigabit MII (GMII) bus, and a Reduced GMII (RMII) bus.

11. The circuit device of claim 9, further comprising a powered device (PD) control circuit coupled to the PHY circuit and adapted to manage power over Ethernet (PoE) PD detection and classification processes.

12. The circuit device of claim 11, further comprising a power regulation circuit to receive power from the I/O interface and to produce a regulated power supply for the processing logic;

wherein the PD control circuit is adapted to control the power regulation circuit.

13. The circuit device of claim 9, wherein the PHY circuit is adapted to negotiate a communications link to the network device independent from the processing logic.

14. The circuit device of claim 9, wherein the processing logic includes a reduced power mode to deactivate selected circuits during periods of inactivity.

15. The circuit device of claim 14, wherein the PHY circuit is adapted to receive a data signal during a period of inactivity and to trigger the processing logic to switch from the reduced power mode to an operating mode in response to receiving the data signal.

16. The circuit device of claim 9, wherein the isolation barrier comprises a digital isolation barrier.

17. The circuit device of claim 16, wherein the digital isolation barrier comprises a chip-scale isolation barrier.

18. A method of providing electrical isolation, the method comprising:

receiving data via multiple channels from an input/output (I/O) interface at a physical transport layer (PHY) circuit of a powered device;

multiplexing the data from the multiple channels into a multiplexed data stream for transmission via an input/output (I/O) interface bus; and

electrically isolating the PHY circuit from media access control (MAC) circuitry coupled to the MII bus via a digital isolation barrier.

19. The method of claim 18, further comprising:

detecting data at the PHY circuit of the powered device; and

triggering the media access control circuitry to switch from a reduced power mode to an operating mode in response to detecting the data.

20. The method of claim 18, further comprising negotiating a communications link between the I/O interface of the powered device and a network device coupled to the I/O interface using the PHY circuit.

21. The method of claim 18, further comprising:

receiving a powered device (PD) detection signal at the I/O interface during a PD detection operation; and

generating a PD signature using a PD control circuit in response to receiving the PD detection signal;

wherein the PD control circuit and the PHY circuit comprise a single integrated circuit package.

22. The method of claim 18, wherein the I/O interface bus comprises a Gigabit media independent interface (GMII) bus.

23. The method of claim 18, wherein the I/O interface bus comprises a Reduced Gigabit media independent interface (RGMII) bus.