HIGH-EFFICIENT ENCRYPTION AND DECRYPTION PROCESSING METHOD FOR IMPLEMENTING SMS4 ALGORITHM

• US 20090323930A1
• Filed: 07/19/2007
• Published: 12/31/2009
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: China Iwncomm Co., Ltd, Iwncomm Company Limited
• Original Assignee: Iwncomm Company Limited
• Inventors: Lu, Jiayin, Huang, Zhenhai, Cao, Jun, Yan, Xiang
• Granted Patent: US 8,204,218 B2
• Time in Patent Office: Days
• US Class Current: 380/28
• CPC Class Codes: H04L 2209/80 Wireless network architectures or network communication protocols for wireless network security H04W12/00
• CPC Class Codes: H04L 9/0625 with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI

Abstract

An encrypting/decrypting processing method for implementing SMS4 algorithm in high efficiency is provided. After preparing constant array, input external data into register section, firstly make primary data conversion and then make secondary data conversion, finally repeat data conversion course until complete all specified data conversion courses and obtain processing result of circulating data encryption/decryption. And it solves the technical problems of data conversion in the background technique that number of circulating times is large and encrypting efficiency is low, simplifying the chip design, largely optimizing integrity of chip signal and being able to improve interference immunity of system and reduce system cost.

Claims

1. An encryption and decryption processing method for implementing SMS4 algorithm in high-efficiency, comprising:

1) preparing a constant array;

configuring a width and depth of the constant array data according to the number of data conversion processing components, data with the same width forming a row;

2) inputting external data to a first data consignation component;

at a triggering clock rising or falling edge of a first clock, transmitting data from the input of the first data consignation component to the output of the first data consignation component;

3) performing a first data conversion processing;

at a triggering clock rising or falling edge of the first clock, transmitting data at a first row of the constant array stored in a constant array storage component (3) to all data conversion components respectively;

in the same triggering clock cycle of the first clock, inputting the data from the output of the first data consignation component to a first data conversion component for data conversion processing;

before a subsequent triggering clock rising or falling edge of a second clock arrives, transmitting by the first data conversion component a conversion processing result to the input of a second data consignation component;

at a triggering clock rising or falling edge of the second clock, transmitting the data from the input of the second data consignation component to the output of the second data consignation component;

in the same triggering clock cycle of the second clock, inputting the data from the output of the second data consignation component to a second data conversion component for data conversion processing;

before a subsequent triggering clock rising or falling edge of the first clock arrives, transmitting a processing result to the input of a third data consignation component;

repeating the first data conversion processing until transmitting by a last data conversion component a processing result to the input of the first data consignation component;

4) performing a second data conversion processing;

at a next triggering clock rising or falling edge of the first clock, transmitting data at a next row of the constant array stored in the constant array storage component (3) to all the data conversion components respectively;

in the same triggering clock cycle of the first clock, inputting the data from the output of the first data consignation component to the first data conversion component for data conversion processing;

before a subsequent triggering clock rising or falling edge of the second clock arrives, transmitting by the first data conversion component a conversion processing result to the input of the second data consignation component;

at a triggering clock rising or falling edge of the second clock, transmitting the data from the input of the second data consignation component to the output of the second data consignation component;

in the same triggering clock cycle of the second clock, inputting the data from the output of the second data consignation component to the second data conversion component for data conversion processing;

before a further triggering clock rising or falling edge of the first clock arrives, transmitting a processing result to the input of the first data consignation component;

5) repeating the second data conversion processing;

repeating the second data conversion processing until all specified data conversion processing is completed so as to obtain a cyclic encryption and decryption data processing result.

2. The encryption and decryption processing method for implementing SMS4 algorithm in high-efficiency according to claim 1, wherein the step 2) further comprises inputting external data to a A data consignation component (101):

at a triggering clock rising or falling edge of a clock A, transmitting data from the input of the A data consignation component (101) to the output of the A data consignation component (101);

the step

     3) of performing a first data conversion processing further comprises;

(3.1) at a triggering clock rising or falling edge of the clock A, transmitting data at a first row of the constant array stored in a constant array storage component (3) to all data conversion components respectively;

(3.2) in the same triggering clock cycle of the clock A, inputting the data from the output of the A data consignation component (101) to a A data conversion component (102) for data conversion processing;

before a subsequent triggering clock rising or falling edge of a clock D arrives, transmitting by the A data conversion component (102) a conversion processing result to the input of a D data consignation component (401);

(3.3) at a triggering clock rising or falling edge of the clock D, transmitting the data from the input of the D data consignation component (401) to the output of the D data consignation component (401);

(3.4) in the same triggering clock cycle of the second clock, inputting the data from the output of the D data consignation component (401) to a D data conversion component (402) for data conversion processing;

before a subsequent triggering clock rising or falling edge of the clock A arrives, transmitting a processing result to the input of the A data consignation component (101);

the step

     4) of performing a second data conversion processing further comprises;

(4.1) at a next triggering clock rising or falling edge of the clock A, transmitting data at a next row of the constant array stored in the constant array storage component (3) to all the data conversion components respectively;

(4.2) in the same triggering clock cycle of the clock A, inputting the data from the output of the A data consignation component (101) to the A data conversion component (102) for data conversion processing;

before a subsequent triggering clock rising or falling edge of the clock D arrives, transmitting by the A data conversion component (102) a conversion processing result to the input of the D data consignation component (401);

(4.3) at a triggering clock rising or falling edge of the clock D, transmitting the data from the input of the D data consignation component (401) to the output of the D data consignation component (401);

(4.4) in the same triggering clock cycle of the clock D, inputting the data from the output of the D data consignation component (401) to the D data conversion component (402) for data conversion processing;

before a further triggering clock rising or falling edge of the clock A arrives, transmitting a processing result to the input of the A data consignation component (101).

3. The encryption and decryption processing method for implementing SMS4 algorithm in high-efficiency according to claim 2, wherein the preparation of the constant array meets the following requirements:

1) constant array data obtained from key extension processing is arranged according to the order of address and stored in the constant array storage component (3);

2) a width and depth is configured according to the number of data conversion processing components in the data conversion processing, with the width multiplied by the depth being 1024;

3) Data with the same width in the constant array forms a row;

a first row of the constant array stored in the constant array storage component (3) refers to a first address of the constant array storage component (3) in the process of encryption;

the first row of the constant array stored in the constant array storage component (3) refers to a last address of the constant array storage component (3) in the process of decryption.

4. The encryption and decryption processing method for implementing SMS4 algorithm in high-efficiency according to claim 3, wherein the frequency of clock A is the same as that of clock D, and there is a fixed phase difference between the clock A and the clock D.

6. The encryption and decryption processing method for implementing SMS4 algorithm in high-efficiency according to claim 2, wherein the phase difference between the clock A and the clock D is 180 degree.

7. The encryption and decryption processing method for implementing SMS4 algorithm in high-efficiency according to claim 1, wherein

the step 2) further comprises inputting external data to a A data consignation component (101):

at a triggering clock rising or falling edge of a clock A, transmitting data from the input of the A data consignation component (101) to the output of the A data consignation component (101);

the step

     3) of performing a first data conversion processing further comprises;

(3.1) at a triggering clock rising or falling edge of the clock A, transmitting data at a first row of the constant array stored in the constant array storage component (3) to all data conversion components respectively;

(3.2) in the same triggering clock cycle of the clock A, inputting the data from the output of the A data consignation component (101) to the A data conversion component (102) for data conversion processing;

before a subsequent triggering clock rising or falling edge of a clock B arrives, transmitting by the A data conversion component (102) the conversion processing result to the input of a B data consignation component (201);

(3.3) at a triggering clock rising or falling edge of the clock B, transmitting the data from the input of the B data consignation component (201) to the output of the B data consignation component (201) respectively;

(3.4) in the same triggering clock cycle of the clock B, inputting the data from the output of the B data consignation component (201) to a B data conversion component (202) for data conversion processing;

before a subsequent triggering clock rising or falling edge of a clock C arrives, transmitting by the B data conversion component (202) a conversion processing result to the input of a C data consignation component (301);

(3.5) at a triggering clock rising or falling edge of the clock C, transmitting the data from the input of the C data consignation component (301) to the output of the C data consignation component (301) respectively;

(3.6) in the same triggering clock cycle of the clock C, inputting the data from the output of the C data consignation component (301) to a C data conversion component (302) for data conversion processing;

before a subsequent triggering clock rising or falling edge of a clock D arrives, transmitting the conversion processing result to the input of a D data consignation component (401);

(3.7) at a triggering clock rising or falling edge of the clock D, transmitting the data from the input of the D data consignation component (401) to the output of the D data consignation component (401) respectively;

(3.8) in the same triggering clock cycle of the clock D, inputting the data from the output of the D data consignation component (401) to a D data conversion component (402) for data conversion processing;

before a subsequent triggering clock rising or falling edge of the clock A arrives, transmitting a processing result to the input of the A data consignation component (101);

the step

     4) of performing a second data conversion processing further comprises;

(4.1) at a next triggering clock rising or falling edge of the clock A, transmitting the data at a next row of the constant array stored in the constant array storage component (3) to all data conversion components respectively;

(4.2) in the same triggering clock cycle of the clock A, inputting the data from the output of the A data consignation component (101) to the A data conversion component (102) for data conversion processing;

before a subsequent triggering clock rising or falling edge of the clock B arrives, transmitting by the A data conversion component (102) a conversion processing result to the input of B data consignation component (401);

(4.3) at a triggering clock rising or falling edge of the clock B, transmitting the data from the input of the B data consignation component (201) to the output of the B data consignation component (201);

(4.4) in the same triggering clock cycle of the clock B, inputting the data from the output of the B data consignation component (201) to the B data conversion component (202) for data conversion processing;

before a subsequent triggering clock rising or falling edge of the clock C arrives, transmitting a processing result to the input of the C data consignation component (301);

(4.5) at a triggering clock rising or falling edge of the clock C, transmitting the data from the input of the C data consignation component (301) to the output of the C data consignation component (301);

(4.6) in the same triggering clock cycle of the clock C, inputting the data from the output of the C data consignation component (301) to the C data conversion component (302) for data conversion processing;

before a subsequent triggering clock rising or falling edge of the clock D arrives, transmitting a processing result to the input of the D data consignation component (401);

(4.7) at a triggering clock rising or falling edge of the clock D, transmitting the data from the input of the D data consignation component (401) to the output of the D data consignation component (401);

(4.8) in the same triggering clock cycle of the clock D, inputting the data from the output of the D data consignation component (401) to the D data conversion component (402) for data conversion processing;

before a further triggering clock rising or falling edge of the clock A arrives, transmitting a processing result to the input of the A data consignation component (101).

8. The encryption and decryption processing method for implementing SMS4 algorithm in high-efficiency according to claim 7, wherein the preparation of the constant array meets the following requirements:

1) constant array data obtained from key extension processing is arranged according to the order of address and stored in the constant array storage component (3);

2) a width and depth is configured according to the number of data conversion processing components in the data conversion processing, with the width multiplied by the depth being 1024;

3) Data with the same width in the constant array forms a row;

a first row of the constant array stored in the constant array storage component (3) refers to a first address of the constant array storage component (3) in the process of encryption;

the first row of the constant array stored in the constant array storage component (3) refers to a last address of the constant array storage component (3) in the process of decryption.

9. The encryption and decryption processing method for implementing SMS4 algorithm in high-efficiency according to claim 7, wherein the clock A, the clock B, the clock C and the clock D have the same frequency, and there is fixed phase differences between the clock A and the clock B, between the clock B and the clock C as well as between the clock C and the clock D.

10. The encryption and decryption processing method for implementing SMS4 algorithm in high-efficiency according to claim 7, wherein the phase differences between the clock A and the clock B, between the clock B and the clock C as well as between the clock C and the clock D are equal to each other.

11. The encryption and decryption processing method for implementing SMS4 algorithm in high-efficiency according to claim 7, wherein the phase differences between the clock A and the clock B, between the clock B and the clock C as well as between the clock C and the clock D are 90 degree.

12. The encryption and decryption processing method for implementing SMS4 algorithm in high-efficiency according to claim 3, wherein the phase difference between the clock A and the clock D is 180 degree.

13. The encryption and decryption processing method for implementing SMS4 algorithm in high-efficiency according to claim 8, wherein the phase differences between the clock A and the clock B, between the clock B and the clock C as well as between the clock C and the clock D are 90 degree.

5. (canceled)