BONDED SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME

• US 20090325343A1
• Filed: 05/29/2009
• Published: 12/31/2009
• Est. Priority Date: 06/24/2003
• Status: Active Grant

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun
• Granted Patent: US 7,799,675 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/0104 Zirconium [Zr]
• CPC Class Codes: H01L 2924/01042 Molybdenum [Mo]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01073 Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A method of forming a bonded semiconductor structure circuit includes providing a support substrate which carries a first semiconductor circuit and providing a first interconnect region carried by the support substrate. The method includes providing a bonded semiconductor substrate which is bonded to the first interconnect region through a bonding interface and forming a second semiconductor circuit which is carried by the first bonded semiconductor substrate.

Claims

1. A method of forming a bonded semiconductor structure circuit, comprising:

providing a support substrate which carries a first semiconductor circuit;

providing a first interconnect region carried by the support substrate, the first interconnect region including a conductive line connected to the first semiconductor circuit, wherein the conductive line includes a refractory metal;

providing a first bonded semiconductor substrate which is bonded to the first interconnect region through a first bonding interface;

forming a second semiconductor circuit which is carried by the first bonded semiconductor substrate;

forming a dielectric layer which is adjacent to a first sidewall of the first bonded semiconductor substrate;

forming a conductive line which extends through the dielectric layer; and

providing a second interconnect region which is carried by the first bonded semiconductor substrate, wherein the second interconnect region is connected to the second semiconductor circuit;

wherein the first and second semiconductor circuits are connected together through the first and second interconnect regions and the conductive line extending through the dielectric layer.

2. The method of claim 1, wherein the first and second semiconductor circuits operate as volatile and non-volatile memory circuits, respectively.

3. The method of claim 1, wherein the first and second semiconductor circuits operate as a memory circuit and control circuit, respectively.

4. The method of claim 1, wherein the first semiconductor circuit includes a vertically oriented semiconductor device and the second semiconductor circuit includes a horizontally oriented semiconductor device.

5. The method of claim 1, wherein the vertically oriented semiconductor device operates as a memory device and the second semiconductor circuit controls the operation of the vertically oriented semiconductor device.

6. The method of claim 4, wherein the vertically oriented semiconductor device includes a layer structure which includes an oxide layer which extends between a silicon layer and a nitride layer.

7. The method of claim 1, wherein the first bonded semiconductor includes crystalline semiconductor material.

8. The method of claim 1, further including providing a second bonded semiconductor substrate which is bonded to the second interconnect region through a second bonding interface.

9. A method of forming a bonded semiconductor structure circuit, comprising:

providing a support substrate;

forming a vertically oriented semiconductor device which is carried by the support substrate;

forming a first interconnect region which is carried by the support substrate and includes a conductive line connected to the vertically oriented semiconductor device;

coupling a first bonded substrate to the first interconnect region through a bonding layer and bonding interface;

forming a first dielectric layer which extends along a sidewall of the first bonded substrate;

forming a conductive line which extends through the first dielectric layer and is connected to the first interconnect region;

forming a first electronic circuit which is carried by the first bonded substrate;

forming a second interconnect region which is carried by the first bonded substrate and connected to the first electronic circuit and the conductive line extending through the first dielectric layer.

10. The method of claim 9, wherein the vertically oriented semiconductor device includes a mesa structure having a stack of semiconductor layers, and a control dielectric region extending annularly around the stack of semiconductor layers.

11. The method of claim 10, wherein the control dielectric region includes an oxide layer and a nitride layer.

12. The method of claim 9, wherein the vertically oriented semiconductor device operates as a memory device and the first semiconductor circuit controls the operation of the vertically oriented semiconductor device.

13. The method of claim 9, wherein the first bonded semiconductor includes crystalline semiconductor material.

14. The method of claim 9, further including providing a second bonded semiconductor substrate which is bonded to the second interconnect region through a second bonding interface.

15. The method of claim 14, further including forming a second dielectric layer which extends along a sidewall of the second bonded substrate.

16. The method of claim 15, further including forming a conductive line which extends through the second dielectric layer and is connected to the second interconnect region.

17. The method of claim 16, further including forming a second electronic circuit which is carried by the second bonded substrate.

18. The method of claim 17, further including forming a third interconnect region which is carried by the second bonded substrate and is connected to the second electronic circuit and the conductive line extending through the second dielectric layer.

19. The method of claim 9, wherein the vertically oriented semiconductor device includes a dual gate.