Method of manufacturing layered chip package

• US 20090325345A1
• Filed: 06/30/2008
• Published: 12/31/2009
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: Headway Technologies Incorporated, TDK Corporation
• Original Assignee: Headway Technologies Incorporated, TDK Corporation
• Inventors: Ito, Hiroyuki, Sueki, Satoru, Harada, Tatsuya, Sasaki, Yoshitaka, Okuzawa, Nobuyuki
• Granted Patent: US 7,767,494 B2
• Time in Patent Office: Days
• US Class Current: 438/109
• CPC Class Codes: H01L 21/67005 Apparatus not specifically provided for elsewhere processes per se H01L21/30, H01L21/46, H01L23/00; simple temporary support means, e.g. using adhesives, electric or magnetic means H01L21/68, H01L21/302
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A manufacturing method for a layered chip package including a stack of a plurality of layer portions includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure. The step of fabricating the layered substructure includes: fabricating a first and a second pre-polishing substructure; bonding the first pre-polishing substructure to a jig such that a first surface of the first pre-polishing substructure faces the jig; forming a first substructure by polishing a second surface of the first pre-polishing substructure; bonding the second pre-polishing substructure to the first substructure such that a first surface of the second pre-polishing substructure faces the polished surface of the first substructure; and forming a second substructure by polishing a second surface of the second pre-polishing substructure.

Claims

1. A method of manufacturing a layered chip package that comprises a plurality of layer portions stacked, each of the plurality of layer portions including a semiconductor chip, the method comprising the steps of:

fabricating a layered substructure by stacking a plurality of substructures in correspondence with the order of stacking of the plurality of layer portions of the layered chip package, wherein the plurality of substructures respectively correspond to the plurality of layer portions of the layered chip package, each substructure including a plurality of its corresponding layer portions and being intended to be cut later at a boundary between every adjacent ones of the plurality of its corresponding layer portions; and

fabricating a plurality of layered chip packages by using the layered substructure, wherein;

the step of fabricating the layered substructure includes;

a step of fabricating a first pre-polishing substructure by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the first pre-polishing substructure having a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer and including a plurality of pre-semiconductor-chip portions aligned, each of the pre-semiconductor-chip portions including a device;

a step of fabricating a second pre-polishing substructure by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the second pre-polishing substructure having a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer and including a plurality of pre-semiconductor-chip portions aligned, each of the pre-semiconductor-chip portions including a device;

a step of bonding the first pre-polishing substructure to a jig such that the first surface of the first pre-polishing substructure faces the jig;

a first polishing step for polishing the second surface of the first pre-polishing substructure bonded to the jig so that the first pre-polishing substructure is thinned by the polishing and thereby a first substructure is formed in a state of being bonded to the jig;

a step of bonding the second pre-polishing substructure to the first substructure such that the first surface of the second pre-polishing substructure faces the polished surface of the first substructure; and

a second polishing step for polishing the second surface of the second pre-polishing substructure so that the second pre-polishing substructure is thinned by the polishing and thereby a second substructure is formed in a state of being stacked on the first substructure.

2. A method of manufacturing a layered chip package, the layered chip package comprising:

a main body having a top surface, a bottom surface and four side surfaces; and

wiring disposed on at least one of the side surfaces of the main body, wherein;

the main body includes a plurality of layer portions stacked;

each of the plurality of layer portions includes;

a semiconductor chip having a top surface, a bottom surface and four side surfaces;

an insulating portion covering at least one of the four side surfaces of the semiconductor chip; and

a plurality of electrodes connected to the semiconductor chip;

the insulating portion has at least one end face located at the at least one of the side surfaces of the main body on which the wiring is disposed;

each of the plurality of electrodes has an end face that is surrounded by the insulating portion and located at the at least one of the side surfaces of the main body on which the wiring is disposed; and

the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions,

the method comprising the steps of;

fabricating a layered substructure by stacking a plurality of substructures in correspondence with the order of stacking of the plurality of layer portions of the layered chip package, wherein the plurality of substructures respectively correspond to the plurality of layer portions of the layered chip package, each substructure including a plurality of its corresponding layer portions and being intended to be cut later at a boundary between every adjacent ones of the plurality of its corresponding layer portions; and

fabricating a plurality of layered chip packages by using the layered substructure, wherein;

the step of fabricating the layered substructure includes;

a step of fabricating a first pre-substructure wafer by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the first pre-substructure wafer having a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer and including a plurality of pre-semiconductor-chip portions aligned, each of the pre-semiconductor-chip portions including a device;

a step of fabricating a second pre-substructure wafer by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the second pre-substructure wafer having a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer and including a plurality of pre-semiconductor-chip portions aligned, each of the pre-semiconductor-chip portions including a device;

a step of fabricating a first pre-polishing substructure having a first surface and a second surface that respectively correspond to the first surface and the second surface of the first pre-substructure wafer, wherein the first pre-polishing substructure is fabricated through;

forming in the first pre-substructure wafer at least one groove that extends to be adjacent to at least one of the pre-semiconductor-chip portions, opens at the first surface of the first pre-substructure wafer and has a bottom that does not reach the second surface of the first pre-substructure wafer;

forming an insulating layer to fill the at least one groove, the insulating layer being intended to become part of the insulating portion later; and

forming the plurality of electrodes such that part of each of the electrodes lies on the insulating layer;

a step of fabricating a second pre-polishing substructure having a first surface and a second surface that respectively correspond to the first surface and the second surface of the second pre-substructure wafer, wherein the second pre-polishing substructure is fabricated through;

forming in the second pre-substructure wafer at least one groove that extends to be adjacent to at least one of the pre-semiconductor-chip portions, opens at the first surface of the second pre-substructure wafer and has a bottom that does not reach the second surface of the second pre-substructure wafer;

forming an insulating layer to fill the at least one groove, the insulating layer being intended to become part of the insulating portion later; and

forming the plurality of electrodes such that part of each of the electrodes lies on the insulating layer;

a step of bonding the first pre-polishing substructure to a jig such that the first surface of the first pre-polishing substructure faces the jig;

a first polishing step for polishing the second surface of the first pre-polishing substructure bonded to the jig so that the first pre-polishing substructure is thinned by the polishing and thereby a first substructure is formed in a state of being bonded to the jig;

a step of bonding the second pre-polishing substructure to the first substructure such that the first surface of the second pre-polishing substructure faces the polished surface of the first substructure; and

a second polishing step for polishing the second surface of the second pre-polishing substructure so that the second pre-polishing substructure is thinned by the polishing and thereby a second substructure is formed in a state of being stacked on the first substructure.

3. The method of manufacturing the layered chip package according to claim 2, wherein:

in the first polishing step, the second surface of the first pre-polishing substructure is polished until the at least one groove of the first pre-polishing substructure becomes exposed; and

in the second polishing step, the second surface of the second pre-polishing substructure is polished until the at least one groove of the second pre-polishing substructure becomes exposed.

4. The method of manufacturing the layered chip package according to claim 2, wherein:

in each of the step of fabricating the first pre-polishing substructure and the step of fabricating the second pre-polishing substructure, an alignment mark is formed on the insulating layer simultaneously with the formation of the plurality of electrodes; and

in the step of bonding the second pre-polishing substructure to the first substructure, alignment of the first substructure and the second pre-polishing substructure is performed using the alignment mark.

5. The method of manufacturing the layered chip package according to claim 4, wherein the insulating layer is transparent.

6. The method of manufacturing the layered chip package according to claim 2, wherein the step of fabricating a plurality of layered chip packages includes the steps of:

forming a main body aggregate by cutting the layered substructure, the main body aggregate including a plurality of pre-main-body portions each of which will later become the main body, the plurality of pre-main-body portions being aligned in one direction that is orthogonal to a stacking direction of the plurality of layer portions;

forming the wiring for each of the pre-main-body portions of the main body aggregate; and

cutting the main body aggregate after the formation of the wiring so as to separate the plurality of pre-main-body portions from each other so that each of them becomes the main body and the plurality of layered chip packages are thereby formed, wherein

in the step of forming the main body aggregate, the insulating layer is cut to form a cut surface along a direction in which the at least one groove extends, whereby part of the at least one end face of the insulating portion is formed by the cut surface of the insulating layer and the end faces of the plurality of electrodes are exposed.

7. The method of manufacturing the layered chip package according to claim 6, wherein, in the step of forming the wiring, a plurality of the main body aggregates are arranged in the stacking direction of the plurality of layer portions and then the wiring is formed for each of the pre-main-body portions of the plurality of main body aggregates.

8. The method of manufacturing the layered chip package according to claim 7, wherein:

in each of the step of fabricating the first pre-polishing substructure and the step of fabricating the second pre-polishing substructure, an alignment mark is formed on the insulating layer simultaneously with the formation of the plurality of electrodes; and

in the step of forming the wiring, alignment of the plurality of main body aggregates to be arranged in the stacking direction of the plurality of layer portions is performed using the alignment mark.

9. The method of manufacturing the layered chip package according to claim 8, wherein the insulating layer is transparent.