PSEUDO-RANDOM NUMBER GENERATION DEVICE, STREAM ENCRYPTION DEVICE AND PROGRAM

• US 20090327382A1
• Filed: 07/18/2007
• Published: 12/31/2009
• Est. Priority Date: 07/25/2006
• Status: Abandoned Application

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Hisakado, Toru
• Application Number:
  US12/374,987
• Publication Number:
  US 20090327382A1
• Time in Patent Office: Days
• US Class Current: 708/252
• CPC Class Codes: G06F 2207/581 Generating an LFSR sequence, e.g. an m-sequence; sequence may be generated without LFSR, e.g. using Galois Field arithmetic
• CPC Class Codes: G06F 2207/7223 Randomisation as countermeasure against side channel attacks
• CPC Class Codes: G06F 2207/7261 Uniform execution, e.g. avoiding jumps, or using formulae with the same power profile
• CPC Class Codes: G06F 7/582 Pseudo-random number generators
• CPC Class Codes: G06F 7/584 using finite field arithmetic, e.g. using a linear feedback shift register
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
• CPC Class Codes: H04L 9/0662 with particular pseudorandom sequence generator

Abstract

A pseudo-random number generation device having a resistance against attack methods that use the number of operations of an LFSR, a stream encryption device, and a program are provided. The stream encryption device has: means (delay means 811 to 81N) which exclusively operate with each LFSR (801 to 80N) in the pseudo-random number generator, that is of a clock control type, and makes uniform the generation processing time or the power consumption of one output unit; or means which randomizes the generation processing time or the power consumption power of one output unit.

Claims

1. A pseudo-random number generation device of a clock control type, comprising:

N linear feedback shift registers, wherein operational control of each of said linear feedback shift registers is performed according to an internal state of each of said linear feedback shift registers, to generate a pseudo-random number, said device further comprising;

a unit that makes uniform generation processing time of one output unit, irrespective of the number of operations of said linear feedback shift registers.

2. The pseudo-random number generation device according to claim 1, further comprising a delay unit for executing delay processing that consumes processing time approximately similar to operation processing of said linear feedback shift registers;

wherein

said generation processing time of one output unit is retained for generation processing time when all said linear feedback shift registers operate, by making said delay means repeatedly operate.

3. The pseudo-random number generation device according to claim 1, further comprising a delay unit for executing delay processing that consumes processing time approximately similar to operation processing of said linear feedback shift registers;

wherein

said generation processing time of one output unit is retained for generation processing time when all said linear feedback shift registers operate, by making said delay means operate exclusively with operation of each of said linear feedback shift registers.

4. The pseudo-random number generation device according to claim 3, further comprising, as said delay means, dummy linear feedback shift registers of a similar number and similar size to said N linear feedback shift registers.

5. The pseudo-random number generation device according to claim 1, further comprising a unit for varying said generation processing time of one output unit, that was made uniform.

15. A stream encryption device comprising said pseudo-random number generation device according to claim 1.

6. A pseudo-random number generation device of a clock control type, comprising:

N linear feedback shift registers, wherein operational control of each of said linear feedback shift registers is performed according to an internal state of each of said linear feedback shift registers, to generate a pseudo-random number, said device further comprising;

a unit that varies generation processing time of one output unit, with a variation range larger than processing time necessary for at least one operation of a linear feedback shift register.

7. The pseudo-random number generation device according to claim 6, further comprising random delay means for executing delay processing that consumes random processing time that does not depend on an input parameter, wherein

said generation processing time of one output unit is varied, by making said random delay means operate.

8. A pseudo-random number generation device of a clock control type, comprising:

N linear feedback shift registers, wherein operational control of each of said linear feedback shift registers is performed according to an internal state of each of said linear feedback shift registers, to generate a pseudo-random number,

said device further comprising;

a unit that makes constant power consumed in generation processing of one output unit.

9. The pseudo-random number generation device according to claim 8, further comprising:

a dummy circuit for consuming power approximately similar to said linear feedback shift registers, wherein

power consumed in generation processing of one output unit is retained as power consumption when all said linear feedback shift registers operate, by making said dummy circuit operate repeatedly.

10. The pseudo-random number generation device according to claim 8, further comprising a dummy circuit for consuming power approximately similar to said linear feedback shift registers, wherein

power consumed in generation processing of one output unit is retained as power consumption when all said linear feedback shift registers operate, by making said dummy circuit operate exclusively with operation of each of said linear feedback shift registers.

11. The pseudo-random number generation device according to claim 10, further comprising, as said dummy circuit, dummy linear feedback shift registers of a similar number and similar size to said N linear feedback shift registers.

12. The pseudo-random number generation device according to claim 8, further comprising a unit for varying said power consumed in generation processing of one output unit, which has been made constant.

13. A pseudo-random number generation device of a clock control type, comprising:

N linear feedback shift registers wherein operational control of each of said linear feedback shift registers is performed according to an internal state of each of said linear feedback shift registers, to generate a pseudo-random number,

said device further comprising;

a unit that varies power consumed in generation processing of one output unit, with a variation range larger than power consumption necessary for at least one operation of a linear feedback shift register.

14. The pseudo-random number generation device according to claim 13, further comprising:

a noise generation source that operates randomly without depending on an input parameter, wherein

said power consumed in generation processing of one output unit is varied, by an operation of said noise generation source.

16. A program implemented in a pseudo-random number generation device of a clock control type, which has N linear feedback shift registers and performs operational control of each of said linear feedback shift registers according to an internal state of each of said linear feedback shift registers, to generate a pseudo-random number, wherein

said program performs a function of making uniform generation processing time of one output unit, irrespective of the number of operations of said linear feedback shift registers.

17. The program according to claim 16, further comprising retaining, in a computer built into said pseudo-random number generation device, said generation processing time of one output unit as generation processing time when all of said linear feedback shift registers operate, by repeatedly executing delay processing that consumes processing time of an approximately similar amount as operation processing of said linear feedback shift registers.

18. The program according to claim 16, further comprising:

retaining, in a computer built into said pseudo-random number generation device, said generation processing time of one output unit as generation processing time when all of said linear feedback shift registers operate, by executing delay processing that consumes processing time of an approximately similar amount as operation processing of said linear feedback shift registers, exclusively with operation of each of said linear feedback shift registers.

19. The program according to claim 18, wherein said generation processing time of one output unit is made uniform by making dummy linear feedback shift registers of a similar number and similar size to said N linear feedback shift registers operate exclusively with operation of each of said linear feedback shift registers.

20. The program according to claim 16, wherein a function is performed of varying said generation processing time of one output unit, which has been made uniform.

21-25. -25. (canceled)