APPARATUS AND METHOD FOR DIRECT MEMORY ACCESS IN A HUB-BASED MEMORY SYSTEM

• US 20090327532A1
• Filed: 04/30/2008
• Published: 12/31/2009
• Est. Priority Date: 07/22/2003
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Granted Patent: US 7,966,430 B2
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4009 with data restructuring

Abstract

A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one of the memory devices of the system memory, and further including a memory device interface for coupling to the memory devices, the memory device interface coupling memory requests to the memory devices for access to at least one of the memory devices. A switch for selectively coupling the link interface and the memory device interface is further included in the memory hub. Additionally, a direct memory access (DMA) engine is coupled through the switch to the memory device interface to generate memory requests for access to at least one of the memory devices to perform DMA operations.

Claims

1-42. -42. (canceled)

43. A memory hub for a memory module having a plurality of memory devices, comprising:

a link interface for receiving memory requests for access to at least one of the memory devices;

at least one memory device interface, each memory device interface having a memory controller and configured to be coupled to respective memory devices, the memory device interface further configured to receive and provide memory requests for the respective memory devices for access thereto;

a switch for selectively coupling the link interface and the memory device interface; and

a direct memory access (DMA) engine coupled through the switch to the memory device interface, the DMA engine operable to generate memory requests for accessing at least one of the memory devices to perform DMA operations and further operable to program status information in the I/O register upon completion of the DMA operations.

44. The memory hub of claim 43 wherein the link interface, the memory device interface, the switch, and the DMA engine are embedded systems residing in a single device.

45. The memory hub of claim 43 wherein the memory device interface comprises:

a memory controller coupled to the switch through a memory controller bus and further coupled to the memory devices through a memory device bus;

a write buffer coupled to the memory controller for storing memory requests directed to at least one of the memory devices to which the memory controller is coupled; and

a cache coupled to the memory controller for storing data provided to the memory devices or retrieved from the memory devices.

46. The memory hub of claim 43 wherein the DMA engine comprises:

an address register for storing a starting memory address for a DMA operation;

a target address location for storing a target address of a location to which data is to be moved in the DMA operation;

a count register for storing a count value indicative of the number of memory locations to be accessed in the DMA operation; and

a next register for storing a value representative of the completion of the DMA operation or representative of a memory address corresponding to a link list including a starting memory address, a count value and a next memory address to be loaded into the address register, the count register, and the next register.

47. A memory module, comprising:

a plurality of memory devices; and

a memory hub, comprising;

a link interface for receiving memory requests for access to at least one of the memory devices;

at least one memory device interface, each memory device interface having a memory controller and configured to be coupled to respective memory devices, the memory device interface further configured to receive and provide memory requests for the respective memory devices for access thereto;

a switch for selectively coupling the link interface and the memory device interface; and

a direct memory access (DMA) engine coupled through the switch to the memory device interface, the DMA engine operable to generate memory requests for accessing at least one of the memory devices to perform DMA operations and further operable to program status information in the I/O register upon completion of the DMA operations.

48. The memory module of claim 47 wherein the memory hub is an embedded system having the link interface, the memory device interface, the switch, and the DMA engine residing in a single device.

49. The memory module of claim 47 wherein the memory device interface comprises:

a memory controller coupled to the switch through a memory controller bus and further coupled to the memory devices through a memory device bus;

a write buffer coupled to the memory controller for storing memory requests directed to at least one of the memory devices to which the memory controller is coupled; and

a cache coupled to the memory controller for storing data provided to the memory devices or retrieved from the memory devices.

50. The memory module of claim 47 wherein the DMA engine comprises:

an address register for storing a starting memory address for a DMA operation;

a target address location for storing a target address of a location to which data is to be moved in the DMA operation;

a count register for storing a count value indicative of the number of memory locations to be accessed in the DMA operation; and

a next register for storing a value representative of the completion of the DMA operation or representative of a memory address corresponding to a link list including a starting memory address, a count value and a next memory address to be loaded into the address register, the count register, and the next register.

51. A memory system, comprising:

a memory bus on which memory requests are provided; and

a plurality of memory modules coupled to the memory bus, each memory module having a plurality of memory devices and a memory hub, the memory hub comprising;

a link interface for receiving memory requests for access to at least one of the memory devices;

at least one memory device interface, each memory device interface having a memory controller and configured to be coupled to respective memory devices, the memory device interface further configured to receive and provide memory requests for the respective memory devices for access thereto;

a switch for selectively coupling the link interface and the memory device interface; and

a direct memory access (DMA) engine coupled through the switch to the memory device interface, the DMA engine operable to generate memory requests for accessing at least one of the memory devices to perform DMA operations and further operable to program status information in the I/O register upon completion of the DMA operations.

52. The memory system of claim 51 wherein the memory hub is an embedded system having the link interface, the memory device interface, the switch, and the DMA engine residing in a single device.

53. The memory system of claim 51 wherein the memory bus comprises a high-speed optical memory bus and wherein the link interface comprises an optical memory bus interface circuit for translating optical signals and electrical signals.

54. The memory system of claim 51 wherein a plurality of memory modules are included in the memory system and a first memory module of the plurality of memory modules is coupled to the memory bus and the remaining memory modules of the plurality are coupled in series with the first memory module.

55. The memory system of claim 51 wherein the memory device interface of the memory hub comprises:

a memory controller coupled to the switch through a memory controller bus and further coupled to the memory devices through a memory device bus;

a write buffer coupled to the memory controller for storing memory requests directed to at least one of the memory devices to which the memory controller is coupled; and

a cache coupled to the memory controller for storing data provided to the memory devices or retrieved from the memory devices.

56. The memory system of claim 51 wherein the DMA engine of the memory hub comprises:

an address register for storing a starting memory address of a memory location in the memory system at which a DMA operation begins;

a target address location for storing a target address of a memory location in the memory system to which data is to be moved in the DMA operation;

a count register for storing a count value indicative of the number of memory locations to be accessed in the DMA operation; and

a next register for storing a value representative of the completion of the DMA operation or representative of a memory address corresponding to a link list including a starting memory address, a count value and a next memory address to be loaded into the address register, the count register, and the next register.

57. A method for executing memory operations in a computer system having a processor, a system controller coupled to the processor, and a system memory having at least one memory module coupled to the system controller through a memory bus, the method comprising:

writing direct memory access (DMA) instructions for executing memory operations in the system memory without processor intervention; and

using a DMA controller located on the memory module and without processor intervention, accessing the DMA instructions and handling execution of the memory operations represented by the instructions using the DMA controller until completion of the memory operations.

58. The method of claim 57 wherein writing DMA instructions comprises:

writing a starting memory address of a memory location in the system memory at which the memory operations begins;

writing a target address of a memory location in the system memory to which data is to be moved in the memory operations;

writing a count value indicative of the number of memory locations to be accessed in the memory operations; and

writing a next memory address value representative of the completion of the memory operations or representative of a memory address corresponding to a link list including a starting memory address, a count value and a next memory address value.

59. The method of claim 57 wherein the system memory comprises a plurality of memory modules and wherein handling execution of the memory operations comprises handling access to a memory location in a first of the plurality of memory modules to read data therefrom and access to a memory location in a second of the plurality of memory modules to write the data.