System and Method for Determining a Bus Address for a Controller Within a Network

• US 20090327540A1
• Filed: 06/30/2008
• Published: 12/31/2009
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: LG Energy Solution Limited (LG Corporation)
• Original Assignee: LG Chem Limited (LG Corporation)
• Inventors: Park, Jong Min, Robertson, David C.
• Granted Patent: US 7,962,661 B2
• Time in Patent Office: Days
• US Class Current: 710/104
• CPC Class Codes: G06F 13/4226 with asynchronous protocol

Abstract

A system and a method for determining a bus address for a controller within a network are provided. The method includes coupling a first set of pins of a wire harness connector to a second set of pins of a PCB connector of the controller. The method further includes sampling voltages of a portion of the first set of pins of the PCB connector to determine a wire harness ID utilizing a microprocessor. The method further includes accessing a look-up table from a memory device to select the bus address for the controller using the wire harness ID utilizing the microprocessor. The look-up table includes a plurality of bus addresses correspondingly associated with a plurality of wire harness IDs. The method further includes storing the selected bus address in the memory device utilizing the microprocessor.

Claims

1. A method for determining a bus address for a controller within a network, comprising:

coupling a first set of pins of a wire harness connector to a second set of pins of a PCB connector of the controller;

sampling voltages of a portion of the first set of pins of the PCB connector to determine a wire harness ID utilizing a microprocessor;

accessing a look-up table from a memory device to select the bus address for the controller using the wire harness ID utilizing the microprocessor, the look-up table includes a plurality of bus addresses correspondingly associated with a plurality of wire harness IDs; and

storing the bus address selected for the controller in the memory device utilizing the microprocessor.

2. The method as in claim 1, wherein the portion of the first set of pins comprises at least a first pin and a second pin, the first pin having a high logic voltage indicating a first bit of the wire harness ID and the second pin having a low logic voltage indicating a second bit of the wire harness ID.

3. The method as in claim 2, wherein the second set of pins comprises at least a first connector pin and a second connector pin, the at least first connector pin and the second connector pin being electrically coupled together by a jumper to set the second pin of the first set of pins to the low logic voltage.

4. A system for determining a bus address within a network, comprising:

a controller having a printed circuit board (PCB), a microprocessor, a memory device, and a PCB connector, the microprocessor coupled to the PCB, the memory device operably coupled to the microprocessor, the memory device having a look-up table with a plurality of bus addresses associated with a plurality of wire harness IDs, the PCB connector having a first set of pins, the PCB connector being coupled to the PCB; and

a wire harness connector having a second set of pins being coupled to the first set of pins, the microprocessor being configured to sample voltages of a portion of the first set of pins of the PCB connector to determine a wire harness ID and further configured to access the look-up table to select the bus address for the controller using the wire harness ID.

5. The system as in claim 4, wherein the microprocessor stores the bus address selected for the controller in the memory device.

6. The system as in claim 4, wherein the portion of the first set of pins comprises at least a first pin and a second pin, the first pin having a high logic voltage indicating a first bit of the wire harness ID and the second pin having a low logic voltage indicating a second bit of the wire harness ID.

7. The system as in claim 6, wherein the second set of pins comprises at least a first connector pin and a second connector pin, the first connector pin and the second connector pin being electrically coupled together by a jumper to set the second pin of the first set of pins to the low logic voltage indicating the second bit of the wire harness ID.

8. The system as in claim 4, wherein a master controller within the network is configured to identify the controller among other controllers within the network using the bus address selected for the controller.