System for and method of hand-off between different communication standards

• US 20090327546A1
• Filed: 01/02/2007
• Published: 12/31/2009
• Est. Priority Date: 03/03/2005
• Status: Abandoned Application

• Current Assignee: ASOCS Ltd.
• Original Assignee: ASOCS Ltd.
• Inventors: Solomon, Doron, Guri, Gaby
• Application Number:
  US11/649,146
• Publication Number:
  US 20090327546A1
• Time in Patent Office: Days
• US Class Current: 710/106
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H04W 36/14 Reselecting a network or an air interface
• CPC Class Codes: H04W 88/06 adapted for operation in multiple networks or having at least two operational modes, e.g. multi-mode terminals

Abstract

An integrated chip for use in processing signals encoded in accordance with either one of at least two communication protocols comprises: reconfigurable architecture capable of being selectively arranged into different configurations, at least one configuration corresponding to each respective protocol so as to implement the functionality of the respective protocol with a predetermined complexity, and an intermediate configuration for implementing the hand-off between a first protocol and a second protocol. The intermediate configuration is arranged so as to simultaneously implement the basic functionality of both the first and second protocols during hand-off, and implementation of at least one of the protocols is of lesser complexity than of the corresponding predetermined complexity associated with separately implementing the other of the protocols. A wireless communication device which utilize the chip in the form of configware, can also include an antenna for receiving or transmitting a signal encoded in accordance with anyone of a plurality of communication protocols; and a baseband processor for processing the signals received or transmitted by the antenna. Finally, a method is described.

Claims

1. An integrated chip for use in processing signals encoded in accordance with either one of at least two communication protocols, comprising:

reconfigurable architecture capable of being selectively arranged into different configurations, at least one configuration corresponding to each respective protocol so as to implement the functionality of the respective protocol with a predetermined complexity, and an intermediate configuration for implementing the hand-off between a first protocol and a second protocol,

wherein the intermediate configuration is arranged so as to simultaneously implement the basic functionality of both the first and second protocols during hand-off, and implementation of at least one of the protocols is of lesser complexity than of the corresponding predetermined complexity associated with separately implementing the other of the protocols.

2. An integrated chip according to claim 1, comprising:

a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and

a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols;

wherein at least some of the same megafunctions are used with algorithms of the one and second protocols.

3. An integrated chip according to claim 1, wherein at least some of the megafunctions are parameterized, the parameters of at least some of the megafunctions are adapted to be dynamically changed depending on the communication protocol.

4. An integrated chip according to claim 3, further including buses interconnecting the megafunctions, and wherein the size of at least some of the buses are adapted to be dynamically changed depending on the communication protocol.

5. An integrated chip according to claim 3, wherein the control signals for changing parameters of the parameterized megafunctions are stored in memory.

6. An integrated chip according to claim 3, wherein the control signals for changing the parameters of the parameterized megafunctions are inserted on-line from outside the chip architecture.

7. An integrated chip according to claim 2, wherein the control signals are stored in memory.

8. An integrated chip according to claim 2, wherein the control signals are inserted on-line from outside the chip architecture.

9. An integrated chip according to claim 2, further including an interconnect network among the megafunctions, and memory for storing a set of signals for reconfiguring the megafunctions and interconnect network between the megafunctions so as to set the parameters and algorithms associated with the protocol of the signals being processed.

10. An integrated chip according to claim 1, further including an analyzer configured so as to determine the protocol of the signal processed by the chip architecture for each the one and second protocols, and apply the necessary control signals so as to configure the switches and interconnect the necessary megafunctions for processing the signals according to the one protocol prior to the hand-off, both the one and second protocols during the hand-off, and the second protocol after the hand-off.

11. An integrated chip according to claim 10, wherein the analyzer is an algorithm performed by the system architecture.

12. An integrated chip according to claim 10, wherein the analyzer is an algorithm for checking the strength of the signals processed by the chip architecture.

13. An integrated chip according to claim 10, wherein the analyzer is responsive to the user input to the system architecture.

14. An integrated chip according to claim 1, further including a control for sensing the protocol of the signal, and operating the switches and configuring the megafunctions accordingly.

15. An integrated chip according to claim 1, wherein at least one protocol implements the same algorithm at different stages of the protocol, as a function of a change in the receipt/transmission conditions.

16. An integrated chip according to claim 1, wherein at least one protocol implements the same algorithm at different megafunctions of the same stage of the protocol as a function of a change in the receipt/transmission conditions.

17. A wireless communication device for use in processing signals encoded in accordance with either one of at least two communication protocols, each defined by a series of algorithms, comprising:

an antenna for receiving or transmitting a signal encoded in accordance with anyone of a plurality of communication protocols;

a baseband processor for processing the signals received or transmitted by the antenna; and

configware comprising;

reconfigurable architecture capable of being selectively arranged into different configurations, at least one configuration corresponding to each respective protocol so as to implement the functionality of the respective protocol with a predetermined complexity, and an intermediate configuration for implementing the hand-off between a first protocol and a second protocol,

wherein the intermediate configuration is arranged so as to simultaneously implement the basic functionality of both the first and second protocols during hand-off, and implementation of at least one of the protocols is of lesser complexity than of the corresponding predetermined complexity associated with separately implementing the other of the protocols.

18. The wireless communication device according to claim 17, wherein the wireless device is a transmitter, and the baseband processor encodes the processed signal in accordance with any one of said protocols prior to transmitting the signal.

19. The wireless communication device according to claim 17, wherein the wireless device is a receiver, and the baseband processor decodes the processed signal in accordance with any one of said protocols after receiving the processed signal.

20. The wireless communication device according to claim 17, wherein the wireless device is adapted to transmit and receive, and the baseband processor is configured to encode the processed signal in accordance with any one of the protocols prior to transmitting an encoded signal, and decode the processed signal in accordance with any one of said protocols after receiving the processed signal.

21. A method of manufacturing an integrated chip with an architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms, comprising creating configware so as to include:

reconfigurable architecture capable of being selectively arranged into separate and different configurations, at least one configuration corresponding to each respective protocol so as to implement the functionality of the respective protocol with a predetermined complexity, and an intermediate configuration for implementing the hand-off between one protocol and a second protocol, wherein the intermediate configuration is arranged so as to simultaneously implement the functionality of both the one and second of the protocols during hand-off, at least one being of a lesser complexity than of the corresponding predetermined complexity associated with separately implementing the at least one protocol.

22. A method according to claim 21, wherein the step of creating configware includes the step of determining various ways to partition the architecture in the intermediate configuration, and selecting the partitioning of the architecture of the intermediate configuration so that the performance loss associated with the intermediate configuration is at a minimum.