SYSTEM AND METHOD OF PROVIDING ELECTRICAL ISOLATION

• US 20090327558A1
• Filed: 06/30/2008
• Published: 12/31/2009
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Landry, D. Matthew, Callahan, Phillip A.
• Granted Patent: US 8,095,710 B2
• Time in Patent Office: Days
• US Class Current: 710/301
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In a particular embodiment, a power sourcing equipment (PSE) device is disclosed that includes a plurality of network input/output (I/O) interfaces adapted to physically and electrically connect to a respective plurality of cables. The PSE device further includes a plurality of driver circuits. Each driver circuit of the plurality of driver circuits is coupled to a respective network I/O interface of the plurality of network I/O interfaces to send and receive data via a respective cable of the respective plurality of cables. Further, the PSE device includes a shared isolation barrier to electrically isolate control circuitry from the plurality of driver circuits.

Claims

1. A power sourcing equipment (PSE) device comprising:

a plurality of network input/output (I/O) interfaces adapted to physically and electrically connect to a respective plurality of cables;

a plurality of driver circuits, each of the plurality of driver circuits adapted to transmit data to and receive data from a respective network I/O interface of the plurality of network I/O interfaces; and

a shared isolation barrier to electrically isolate control circuitry from the plurality of driver circuits.

2. The circuit device of claim 1, wherein the shared isolation barrier comprises:

a first SERDES (serializer/deserializer) circuit coupled to the plurality of driver circuits;

a second SERDES circuit coupled to the control circuitry; and

a digital isolation barrier including a first terminal coupled to the first SERDES circuit and including a second terminal coupled to the second SERDES circuit.

3. The circuit device of claim 1, wherein the shared isolation barrier comprises:

a first parallel input/output (I/O) interface coupled to the plurality of driver circuits;

a second parallel I/O interface coupled to the control circuitry; and

a digital isolation barrier including a first terminal coupled to the first parallel I/O interface and including a second terminal coupled to the second parallel I/O interface.

4. The circuit device of claim 1, further comprising a power sourcing equipment (PSE) control circuit coupled to the plurality of driver circuits without electrical isolation, the PSE control circuit adapted to perform powered device detection by applying a powered device detection signal to a selected network I/O interface of the plurality of network I/O interfaces and by detecting a responsive signal at the selected network I/O interface to determine whether a powered device is coupled to the selected network I/O interface.

5. The circuit device of claim 1, further comprising a plurality of capacitors to block a direct current (DC) between the plurality of I/O interfaces and the plurality of driver circuits without blocking data.

6. The circuit device of claim 1, wherein each driver circuit of the plurality of driver circuits is coupled to a respective network I/O interface by multiple wire pairs.

7. The circuit device of claim 6, further comprising:

a power injector to provide a direct current power supply; and

a plurality of choke circuits coupled between wire pairs of the multiple wire pairs and adapted to couple the power injector to the wire pairs, the plurality of choke circuits to provide alternating current (AC) blocking to prevent power supply noise from interfering with data flow and to reduce attenuation of data signal amplitude by a power supply ground while allowing direct current to flow to the plurality of network I/O interfaces.

8. The circuit device of claim 7, further comprising a power sourcing equipment (PSE) circuit adapted to control the power injector to selectively provide a power supply to one or more of the plurality of network I/O interfaces.

9. A system comprising:

a network I/O interface adapted to couple to a cable having multiple wires to carry power and data;

a physical transport (PHY) circuit including transmit and receive circuitry coupled to the network I/O interface via multiple wire pairs to send and receive data via the Ethernet cable;

a power supply circuit coupled to the network I/O interface and adapted to apply power to the cable via the network I/O interface; and

an isolation barrier coupled between the physical transport circuit and control circuitry to electrically isolate the control circuitry from the PHY circuit without isolating the PHY circuit from the network I/O interface.

10. The system of claim 9, further comprising a direct current (DC) block circuit between the PHY circuit and the network I/O interface to prevent a direct current from reaching the PHY circuit from the network I/O interface while allowing data to pass.

11. The system of claim 10, wherein the DC block circuit comprises one or more capacitors.

12. The system of claim 9, further comprising choke circuitry including inductor pairs coupled between wires of the multiple wire pairs, the choke circuitry to couple the power injector circuit to the multiple wire pairs and to block alternating current (AC) flow to prevent disruption of the data.

13. The system of claim 9, further comprising a switching field effect transistor (FET) responsive to the control circuitry to selectively apply the power to the cable.

14. The system of claim 9, wherein the isolation barrier comprises a digital isolation barrier, the system further comprising:

a first multiplexer circuit coupled to the PHY circuit via a media independent (MII) interface and coupled to a first terminal of the digital isolation barrier; and

a second multiplexer circuit coupled to the control circuit via a second media independent (MII) interface and to a second terminal of the digital isolation barrier;

wherein the first and second multiplexer circuits are adapted to transmit MII signals across the digital isolation barrier.

15. The system of claim 9, further comprising power sourcing equipment (PSE) circuitry coupled to the PHY circuit without isolation, the PSE circuitry adapted to perform powered device detection and classification operations to detect and determine a power requirement of a powered device coupled to the network I/O interface.

16. The system of claim 9, wherein the PHY circuit, the isolation barrier, and the control circuitry comprise a single integrated circuit package.

17. A method of providing electrical isolation, the method comprising:

sending data to a powered device via an input/output (I/O) interface using a transceiver circuit;

concurrently providing a power supply to the powered device via the I/O interface; and

electrically isolating the transceiver circuit from a control circuit via a digital isolation circuit coupled between the transceiver circuit and the control circuit.

18. The method of claim 17, further comprising:

sending data to a second powered device via a second I/O interface using a second transceiver circuit;

concurrently providing a second power supply to the second powered device via the second I/O interface; and

electrically isolating the second transceiver circuit from the control circuit via the digital isolation circuit.

19. The method of claim 18, wherein the transceiver circuit and the second transceiver circuit are coupled to the digital isolation circuit via a multiplexer circuit.

20. The method of claim 17, further comprising blocking a direct current (DC) signal from reaching the transceiver circuit using one or more capacitors.

21. The method of claim 17, wherein the transceiver circuit and the control circuit are integrated in a single integrated circuit package.