BIMODAL MEMORY CONTROLLER

• US 20090327565A1
• Filed: 06/12/2009
• Published: 12/31/2009
• Est. Priority Date: 06/27/2008
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A.
• Granted Patent: US 7,961,532 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory controller has a communication path which is coupled to an external, wired electrical path. The memory controller includes at least two alternative interface circuits to communicate with the external, wired electrical path using signals having one of two different formats. Each of the alternative interface circuits is electrically coupled to a corresponding signal connector, and only one of these signal connectors, in turn, is electrically coupled to the external path via an I/O pin or printed-circuit board connection (depending upon implementation). The remaining signal connector may be left electrically uncoupled from the external, wired electrical path, and, if desired, the corresponding remaining interface circuit may be left unused during operation of the memory controller.

Claims

1. A memory controller having a communication path that is to be coupled to an external, wired electrical path, the memory controller comprising:

a first interface circuit, electrically coupled to the communication path, to communicate with the external, wired electrical path using signals of a first format;

a first signal connector electrically coupled to the first interface circuit;

a second, alternative interface circuit, electrically coupled to the communication path, to communicate with the external, wired electrical path using signals of a second format; and

a second signal connector electrically coupled to the second, alternative interface circuit;

wherein the memory controller is adapted to selectively electrically couple only one of the first signal connector with the external, wired electrical path or the second signal connector to the external, wired electrical path, while the other of the first signal connector or the second signal connector is adapted to be left electrically uncoupled with the external, wired electrical path.

2. The memory controller of claim 1, wherein the first interface circuit includes first driver and receiver circuits;

and

wherein the second, alternative interface circuit includes second driver and receiver circuits that are separate from the first driver and receiver circuits.

3. The memory controller of claim 2, wherein the second driver and receiver circuits have a lower voltage swing and a larger data rate than the first driver and receiver circuits.

4. The memory controller of claim 2, wherein the second driver and receiver circuits have less input/output (I/O) capacitance than the first driver and receiver circuits.

5. The memory controller of claim 2, wherein the driver circuits of the first interface circuit and the second, alternative interface circuit have different breakdown voltages.

6. The memory controller of claim 2, wherein the first interface circuit and the second, alternative interface circuit have different electrostatic-discharge protection circuits.

7. The memory controller of claim 2, wherein the driver circuits of the first interface circuit include single-ended drivers and the driver circuits of the second, alternative interface circuit include differential drivers.

8. The memory controller of claim 1, wherein the first signal connector is included in a first set of signal connectors and the second signal connector is included in a second set of signal connectors;

wherein the first set of signal connectors and the second set of signal connectors are arranged in pairs; and

wherein the first set of signal connectors and the second set of signal connectors have a common connector pitch that is adapted to accommodate a single bonding wire for a given connector in a given pair of connectors.

9. The memory controller of claim 1, further comprising a state-specifying component that specifies which of the first interface circuit and the second, alternative interface circuit is to be used during operation of the memory controller.

10. The memory controller of claim 9, wherein the state-specifying device includes one of a mode register, a fuse, a connector that is to receive a voltage corresponding to a state, or a node to electrically couple to an initialization bus to receive state-specifying information.

11. The memory controller of claim 1, further comprising control logic to determine which of the first signal connector or the second signal connector are electrically coupled to the external, wired electrical path, to activate the corresponding one of the first interface circuit and the second, alternative interface circuit, and to deactivate the remaining interface circuit.

12. The memory controller of claim 1, wherein the first signal connector and the second signal connector are adapted to selectively electrically coupled with the external, wired electrical path via a bonding wire.

13. The memory controller of claim 1, wherein the first signal connector and the second signal connector are adapted to selectively electrically coupled with the external, wired electrical path via a solder ball.

14. The memory controller of claim 1, wherein the first signal connector is included in a first set of signal connectors and the second signal connector is included in a second set of signal connectors;

and

wherein the first interface circuit and the second interface circuit are adapted to provide alternate formats to lines in at least a portion of an I/O bus, which includes the external, wired electrical path.

15. The memory controller of claim 1, wherein the memory controller includes an integrated circuit and a package that uniquely electrically couples only one of the first signal connector or the second signal connector to the external, wired electrical path through a single associated printed-circuit-board mounting connector.

16. The memory controller of claim 15, wherein solder balls electrically couple the first signal connector and the second signal connector to the package;

and

wherein the package electrically couples only one of first signal connector or the second signal connector to the single printed-circuit-board mounting connector.

17. A memory system, comprising:

a memory device;

an external, wired electrical path electrically coupled to the memory device; and

a memory controller, electrically coupled to the external, wired electrical path, wherein the memory controller has an internal communication path, and wherein the memory controller includes;

a first interface circuit, electrically coupled to the internal communication path, to communicate with the external, wired electrical path using signals of a first format;

a first signal connector electrically coupled to the first interface circuit;

a second, alternative interface circuit, electrically coupled to the internal communication path, to communicate with the external, wired electrical path using signals of a second format; and

a second signal connector electrically coupled to the second, alternative interface circuit, wherein the only one of the first signal connector or the second signal connector is selectively electrically coupled with the external, wired electrical path, while the other of the first signal connector or the second signal connector is left electrically uncoupled with the external, wired electrical path.

18. The memory system of claim 17, further comprising a circuit board, wherein the solder balls electrically coupled the circuit board to the first signal connector and the second signal connector;

and

wherein the circuit board electrically couples only one of first signal connector or the second signal connector to the external, wired electrical path.

19. A memory system, comprising:

a memory device;

an external, wired electrical path electrically coupled to the memory device; and

a memory controller, electrically coupled to the external, wired electrical path, wherein the memory controller has an internal communication path, and wherein the memory controller includes;

a first interface circuit, electrically coupled to the internal communication path, to communicate with the external, wired electrical path using signals of a first format;

a second interface circuit, electrically coupled to the internal communication path, to communicate with the external, wired electrical path using signals of a second format; and

means for electrically coupling one of the first interface circuit or the second interface circuit with the external path and for leaving the other of the first signal connector or the second signal connector left electrically uncoupled with the external path.

20. A method for assembling a memory system, comprising:

providing a first set of signal connectors and corresponding first interface circuits to electrically couple at least part of a memory-controller I/O bus in a memory controller to at least part of an external, memory-system I/O bus;

providing a second, alternative set of signal connectors and corresponding second interface circuits to electrically couple at least the part of the memory-controller I/O bus in a memory controller to at least the part of the external, memory-system I/O bus; and

selectively electrically coupling the memory-controller I/O bus with the external, memory-system I/O bus using only one of the first set of signal connectors and the second set of signal connectors based on communication characteristics of the memory system, wherein the remaining set of signal connectors remains selectively electrically uncoupled from the external, memory-system I/O bus.

21. The method of claim 20, wherein remaining interface circuits, which corresponds to the remaining set of signal connectors, remains unused during operation of the memory controller.

22. The method of claim 20, wherein the selective electrical coupling involves selectively electrically coupling only one of the first set of signal connectors and the second set of signal connectors to a single set of printed-circuit-board contacts.

23. The method of claim 20, wherein the selective electrical coupling involves selectively mounting the memory controller to one of at least two alternative packages;

and

wherein a given package is adapted to route communication signals between the external, memory-system I/O bus and exactly one of the first set of signal connectors and the second set of signal connectors.

24. The method of claim 20, wherein the memory-system I/O bus includes at least some lines that are bidirectional.

25. A package to mount a single memory controller onto a printed circuit board that includes a memory-system I/O bus using an alternative one of at least two different communication formats, the package comprising:

a plurality of controller bonding connectors adapted for electrical connection with the single memory controller, the plurality of bonding connectors including at least two alternative sets of connectors, each set including a connector that corresponds to one line of at least part of the memory-system I/O bus; and

a plurality of printed-circuit-board bonding connectors, electrically coupled to at least one of the alternative sets of bonding connectors, to couple the at least one of the alternative sets of bonding connectors with the at least part of the memory system I/O bus.

26. The package of claim 25, wherein the package is specific to a communication format and uniquely electrically couples one set of controller bonding connectors with the at least part of the memory-system I/O bus, and which does not electrically couple the other sets of bonding connectors with the at least part of the memory-system I/O bus.

27. A memory controller, comprising:

a first interface circuit to communicate first signals, having a first communication format, with an external, wired electrical path; and

a second interface circuit to communicate second signals, having a second communication format, via the external, wired electrical path;

wherein, during operation of the memory controller, only one of the first interface circuit and the second interface circuit communicates corresponding signals, via the external, wired electrical path.

28. The memory controller of claim 27, wherein the memory controller automatically determines which of the first interface circuit and the second interface circuit is electrically coupled to the external, wired electrical path.

29. A method of operating a memory controller, comprising:

identifying which of a first interface circuit and a second interface circuit to use to communicate signals via an external, electrical path, wherein the first interface circuit communicates first signals having a first communication format and the second interface circuit communicates second signals having a second communication format; and

communicating with the external electrical path using the identified interface circuit.