NAND MEMORY

• US 20090327581A1
• Filed: 06/30/2008
• Published: 12/31/2009
• Est. Priority Date: 06/30/2008
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Coulson, Richard L.
• Application Number:
  US12/165,319
• Publication Number:
  US 20090327581A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 2029/0407 on power on

Abstract

Disclosed herein is a method and apparatus to refresh/rewrite the data in a NAND solid state storage device (“SSD”) only when it needs to be re-written. Upon power-up, the SSD assumes that it may have been a long time since some of its data was last written, and a background task to scan through all the data is started in the SSD. During idle periods, the entire contents of the drive is read. If a location is read and it has more than “bit error threshold” bits (for example three (3) bits if there is capability to correct eight (8) bits) in error before error correction is applied, it is assumed that this memory location is retaining the data only marginally, and the corrected data should be re-written to a new location, or alternatively re-written in the same location. The corrected data is then re-written to a new location or the same location.

Claims

1. Apparatus comprising:

a NAND memory device including a plurality of NAND memory locations each including a plurality of cells holding at least one charge used to represent one or more data bits of a page of data stored in the memory device;

at least one memory refresh component active at least in part upon initialization or start up of the NAND memory device to;

read one or more of the NAND memory locations storing data in the page stored in the memory device; and

determine the number of data bits that are no longer reliable and, if more than a threshold number of bits are no longer reliable, refreshing the respective memory location by re-writing all or part of the page containing the data bits using the same location or rewriting all or part of the page to a new location in the flash memory.

2. Apparatus according to claim 1 wherein the refresh component is a circuit and/or programmed computer.

3. Apparatus according to claim 1 further wherein the threshold number of bits is equal to a number less than or equal to the maximum number of bits that can be in error before error correction for the memory location is no longer effective.

8. Apparatus according to claim 1 wherein the pages are re-written during at least a portion of the time that the memory device is idle.

4. A method comprising:

upon initialization or start up of a flash memory having NAND memory locations,

a) read one or more NAND pages stored in one or more groups of memory locations that include error correction information;

b) determine the number of data bits of a location that are no longer reliable; and

c) if more than a threshold number of bits are no longer reliable refreshing the respective memory location by re-writing all or part of the page containing the data bits in the same location or re-writing all or part of the page to a new location in the flash memory.

5. A method according to claim 4 further including setting the threshold number of bits to a number less than or equal to the maximum number of bits that can be in error before error correction for the memory location is no longer effective.

9. A method according to claim 4 wherein the pages are re-written during at least a portion of the time the memory is idle.

6. Apparatus comprising:

an electronic system including a microprocessor and at least one NAND memory device;

the NAND memory device including;

a plurality of NAND memory locations each including a plurality of cells holding at least one charge used to represent one or more data bits of a page of data stored in the memory device;

at least one memory refresh component active at least in part upon initialization or start up of the NAND memory device to;

read one or more of the NAND memory locations storing data in the page stored in the memory device; and

determine the number of data bits of that are no longer reliable and, if more than a threshold number of bits are no longer reliable, refreshing the respective memory location by re-writing all or part of the page containing the data bits using the same location or rewriting all or part of the page to a new location in the flash memory.

7. Apparatus according to claim 6 wherein the refresh component is a circuit and/or programmed computer.