MULTI-CORE ENGINE FOR DETECTING BIT ERRORS

• US 20090327818A1
• Filed: 04/27/2007
• Published: 12/31/2009
• Est. Priority Date: 04/27/2007
• Status: Active Grant

• Current Assignee: NetApp, Inc.
• Original Assignee: Network Appliance Incorporated (NetApp, Inc.)
• Inventors: KOGELNIK, CHRISTOPH
• Granted Patent: US 8,898,536 B2
• Time in Patent Office: Days
• US Class Current: 714/49
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 2221/2107 File encryption
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H04L 2463/062 applying encryption of the keys
• CPC Class Codes: H04L 63/0428 wherein the data content is protected, e.g. by encrypting or encapsulating the payload

Abstract

The following description includes a method and a system of detecting bit errors in a multi-core processor. When a subatomic particle, or other matter, impacts the processing cores of the processor, bit flips may occur. To detect these bit flips and thereby prevent erroneous results, operations performed by one core are inversely performed by another core. By comparing the results of the original operation and the inverse operation, embodiments of the invention can detect errors in binary data. If an error is detected, then the operations are performed again. Alternatively, multiple cores do not perform inverse operations, but instead perform identical operations in parallel. The results from the parallel operations are compared and if the results are not identical, then the operations are repeated.

Claims

1. A computing system for detecting errors during computation, comprising:

a plurality of processing cores of a processor of the computing system, wherein a first processing core of the processor and a second processing core of the processor perform inverse computations; and

at least one buffer of the computing system for storing fingerprint information relating to data processed by the first processing core and the second processing core, wherein differences in fingerprint information result in detecting errors.

2. The computing system of claim 1, wherein the first processor core performs an encryption operation and the second processor core performs a decryption operation.

3. The computing system of claim 1, wherein the first processor core performs a compression operation and the second processor core performs a decompression operation.

4. The computing system of claim 1, wherein the fingerprint information is produced from data processed by one of the first processor core and the second processor core.

5. The computing system of claim 4, wherein the fingerprint information is one of parity information, a cyclic redundancy code, a hash function computation, and a linear feedback shift register computation.

6. A method for detecting errors during processor computation, comprising:

determining a first checksum value of a first data block preceding the performance of a first processor core computation;

determining a second checksum value of a second data block after the performance of a second processor core computation; and

comparing the first checksum and the second checksum to detect an error.

7. The method of claim 6, wherein the first processor core computation is an inverse operation of the second processor core computation.

8. The method of claim 7, wherein the first processor core computation is compression and the second processor core computation is decompression.

9. The method of claim 7, wherein the first processor core computation is encryption and the second processor core computation is decryption.

10. The method of claim 6, wherein the first processor core computation is a parallel operation of the second processor core computation.

11. The method of claim 6, wherein the checksum is a signature.

12. The method of claim 11, wherein the signature is one of parity information, a cyclic redundancy code, a hash function computation, and a linear feedback shift register computation.

13. A device, comprising:

a processor including a plurality of buffers, the buffers capable of storing a first signature and a second signature, wherein the processor further includes

a first computing engine operable to perform a computation to determine the first signature;

a second computing engine operable to perform a computation to determine the second signature, wherein the first signature and the second signature are compared to detect whether an error occurred in producing data.

14. The device of claim 13, wherein the first computing engine performs an encryption operation and the second computing engine performs a decryption operation.

15. The device of claim 13, wherein the first computing engine performs a compression operation and the second computing engine performs a decompression operation.

16. The device of claim 13, wherein the first signature and the second signature are identical if no error occurred during computation within the processor.

17. The device of claim 16, wherein the first signature is one of parity information, a cyclic redundancy code, a hash function computation, and a linear feedback shift register computation.

18. The device of claim 16, wherein the second signature is determined using the same method to determine the first signature.

19. An apparatus, comprising:

a processor, including a plurality of buffers, the buffers capable of storing a plurality of signatures, wherein the processor further includes

a plurality of computing engines, wherein a first computing engine of the plurality of computing engines produces data used to determine a first signature, and wherein

a second computing engine of the plurality of computing engines produces data used to determine a second signature, wherein the first and second signatures are compared to detect whether an error occurred in producing data.

20. The apparatus of claim 19, wherein at least one of the plurality of computing engines is one of a field programmable gate array and an application specific integrated circuit.

21. The apparatus of claim 19, wherein the first signature and the second signature are identical if no error occurred during computation within the processor.